View EP1SGX10FF1020C6ES_7067268.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

altera corporation section i?1 preliminary section i. stratix gx device family data sheet this section provides the data sheet specifications for stratix ? gx devices. it contains feature defini tions of the internal architecture, configuration information, testing information, dc operating conditions, and ac timing parameters. this section includes the following chapters: chapter 1, introduction to the stratix gx device data sheet chapter 2, stratix gx transceivers chapter 3, source-synchronous signaling with dpa chapter 4, stratix gx architecture chapter 5, configuration & testing chapter 6, dc & switching characteristics chapter 7, reference & ordering information
section i?2 altera corporation preliminary stratix gx device family data sheet stratix gx device handbook, volume 1 revision history the table below shows th e revision history for chapters 1 through 7 . chapter(s) date / vers ion changes made comments 1 february 2005, v1.0 initial release. 2 june 2006, v1.1 updated ?serial loopback? section. updated figures 2?1 through 2?3 . updated figure 2?13 . updated figures 2?26 and 2?27 . february 2005, v1.0 initial release. 3 august 2005, v1.1 added note (3) to figure 3-7. 4 february 2005, v1.0 initial release. 5 february 2005, v1.0 initial release. 6 june 2006, v1.2 updated ?operating conditions? section. updated table 6?4 . updated note 3 in table 6?6 . added note 12 in table 6?7 . updated figure 6?1 . added figure 6?2 . updated tables 6?13 through 6?16 . changed v od to v id for receiver input voltage and refclkb input voltage in table 6?4 . changed value for undershoot during transition from -0.5 v to -2.0 v in note 3 of ta b l e 6 ? 6 . changed value of v ocm from mv to v in table 6?15 . changed unit value of w to .. august 2005, v1.1 updated tables 6-7 and 6-50. 7 february 2005, v1.0 initial release.
altera corporation 1?1 february 2005 1. introduction to the stratix gx device data sheet overview the stratix ? gx family of devices is altera?s second fpga family to combine high-speed serial transceivers with a scalable, high-performance logic array. stratix gx devices include 4 to 20 high-speed transceiver channels, each incorporating clock da ta recovery (cdr) technology and embedded serdes capability at data rates of up to 3.1875 gigabits per second (gbps). these transceivers are grouped by four-channel transceiver blocks, and are design ed for low power consumption and small die size. the stratix gx fpga te chnology is built upon the stratix architecture, and offers a 1.5-v logi c array with unmatched performance, flexibility, and time-to-market capabilities. this scalable, high-performance architecture makes stratix gx devices ideal for high-speed backplane interface, chip-to-chip, and communications protocol-bridging applications. features transceiver block features are as follows: high-speed serial tr ansceiver channels with cdr provides 500-megabits per second (mbps) to 3.1875-gbps full-duplex operation devices are available with 4, 8, 16, or 20 high-speed serial transceiver channels providing up to 127.5 gbps of full-duplex serial bandwidth support for transceiver-based protocols, including 10 gigabit ethernet attachment unit interface (xaui), gigabit ethernet (gige), and sonet/sdh compatible with pci express, smpte 292m, fibre channel, and serial rapidio i/o standards programmable differential output voltage (v od ), pre-emphasis, and equalization settings for improved signal integrity individual transmitter and receiver channel power-down capability implemented auto matically by the quartus ? ii software for reduced power cons umption during non-operation programmable transceiver-to-fpga interface with support for 8-, 10-, 16-, and 20-bit wide data paths 1.5-v pseudo current mode logic (pcml) for 500 mbps to 3.1875 gbps support for lvds, lvpecl, and 3.3-v pcml on reference clocks and receiver input pins (ac-coupled) built-in self test (bist) hot insertion/removal protection circuitry sgx51001-1.0
1?2 altera corporation stratix gx device handbook, volume 1 february 2005 features pattern detector and word aligner supports programmable patterns 8b/10b encoder/decoder performs 8- to 10-bit encoding and 10- to 8-bit decoding rate matcher compliant with ieee 802.3-2002 for gige mode and with ieee 802-3ae for xaui mode channel bonding compliant with ieee 802.3ae (for xaui mode only) device can bypass some transcei ver block features if necessary fpga features are as follows: 10,570 to 41,250 logic el ements (les); see table 1?1 up to 3,423,744 ram bits (427,96 8 bytes) available without reducing logic resources trimatrix ? memory consisting of three ram block sizes to implement true dual-port memo ry and first-in-out (fifo) buffers up to 16 global clock networks with up to 22 regional clock networks per device region high-speed dsp blocks provide dedicated implementation of multipliers (faster than 300 mhz), mul tiply-accumulate functions, and finite impu lse response (fir) filters up to eight general usage phase-locked loops (four enhanced plls and four fast plls) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time pll reconfiguration, and advanced multiplication and phase shifting support for numerous single-ended and differential i/o standards high-speed source-synchronous differential i/o support on up to 45 channels for 1-gbps performance support for source-synchronous bus standards, including 10-gigabit ethernet xsbi, parallel rapidio, utopia iv, network packet streaming interface (npsi), hypertransport tm technology, spi-4 phase 2 (pos-phy level 4), and sfi-4 support for high-speed external memory, including zero bus turnaround (zbt) sram, quad data rate (qdr and qdrii) sram, double data rate (ddr) sdram, ddr fast cycle ram (fcram), and single data rate (sdr) sdram support for multiple intellectual property megafunctions from altera ? megacore ? functions and altera megafunction partners program (ampp sm ) megafunctions support for remote configuration updates dynamic phase alignment on lvds receiver channels
altera corporation 1?3 february 2005 stratix gx device handbook, volume 1 introduction to the stratix gx device data sheet stratix gx devices are available in space-saving fineline bga ? packages (refer to tables 1?2 and 1?3 ), and in multiple speed grades (refer to table 1?4 ). stratix gx devices support vert ical migration within the same package (that is, you can migrate between the ep1sgx10c and ep1sgx25c devices in the 672-pin fineline bga package). see the stratix gx device pin tables for more information. vertical migration means that you can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. for i/o pin migration across densities, you must cross-reference the available i/o pins using the device pin-outs for all planned densities of a given package type, to identify which i/o pins it is possible to migrate. the quartus i i software can automatically cross reference and place all pins for migr ation when given a device migration list. table 1?1. stratix gx device features feature ep1sgx10c ep1sgx10d ep1sgx25c ep1sgx25d ep1sgx25f ep1sgx40d ep1sgx40g les 10,570 25,660 41,250 transceiver channels 4, 8 4, 8, 16 8, 20 source-synchronous channels 22 39 45 m512 ram blocks (32 18 bits) 94 224 384 m4k ram blocks (128 36 bits) 60 138 183 m-ram blocks (4k 144 bits) 1 2 4 total ram bits 920,448 1,944,576 3,423,744 digital signal processi ng (dsp) blocks 6 10 14 embedded multipliers (1) 48 80 112 plls 4 4 8 note to ta b l e 1 ? 1 : (1) this parameter lists the total number of 9- 9-bit multipl iers for each device. for the total number of 18- 18-bit multipliers per device, divide the total number of 9- 9-b it multipliers by 2. for the total number of 36- 36-bit multipliers per device, decide the tota l number of 9- 9-bit multipliers by 8. table 1?2. stratix gx package options & i/o pin counts (part 1 of 2) note (1) device 672-pin fineline bga 1,020-pin fineline bga ep1sgx10c 362 ep1sgx10d 362 ep1sgx25c 455
1?4 altera corporation stratix gx device handbook, volume 1 february 2005 high-speed i/o interface functional description high-speed i/o interface functional description the stratix gx device family suppor ts high-speed serial transceiver blocks with cdr circuitry as well as source-synchronous interfaces. the channels on the right side of th e device use an embedded circuit dedicated for receiving and transmitting high-speed serial data streams to and from the system board. th ese channels are clustered in a four-channel serial transceiver buil ding block and deliver high-speed bidirectional point-to-point data transmissions to provide up to 3.1875 gbps of full-duplex data transm ission per channe l. the channels on the left side of the device suppo rt source-synchrono us data transfers at up to 1 gbps using lvds, lvpecl, 3.3-v pcml, or hypertransport technology i/o standards. figure 1?1 shows the stratix gx i/o blocks. the differential source-synchronous serial interface and the high-speed serial interface are described in the stratix gx transceivers chapter of the stratix gx device handbook, volume 1 . ep1sgx25d 455 607 ep1sgx25f 607 ep1sgx40d 624 ep1sgx40g 624 note to ta b l e 1 ? 2 : (1) the number of i/o pins listed for each package includes dedicated clock pins and dedicated fast i/o pins. however, these numbers do not include high-speed or clock reference pins for high-speed i/o standards. table 1?3. stratix gx fineline bga package sizes dimension 672 pin 1,020 pin pitch (mm) 1.00 1.00 area (mm 2 ) 729 1,089 length width (mm mm) 27 27 33 33 table 1?4. stratix gx device speed grades device 672-pin fineline bga 1,020-pin fineline bga ep1sgx10 -5, -6, -7 ep1sgx25 -5, -6, -7 -5, -6, -7 ep1sgx40 -5, -6, -7 table 1?2. stratix gx package options & i/o pin counts (part 2 of 2) note (1) device 672-pin fineline bga 1,020-pin fineline bga
altera corporation 1?5 february 2005 stratix gx device handbook, volume 1 introduction to the stratix gx device data sheet figure 1?1. stratix gx i/o blocks note (1) notes to figure 1?1 : (1) figure 1?1 is a top view of the stratix gx silicon die. (2) banks 9 through 12 are enhanced pll external clock output banks. (3) if the high-speed differential i/o pins are not used for high-speed differential signaling, they can support all of the i/o standards except hstl class i and ii, gtl, sstl-18 class ii, pci, pci-x, and agp 1/2. (4) for guidelines for placing single-ended i/o pads next to differential i/o pads, see the selectable i/o standards in stratix & stratix gx devices chapter of the stratix gx device ha ndbook, volume 2 . (5) these i/o banks in stratix gx de vices also support the lvds, lvpecl , and 3.3-v pcml i/o standards on reference clocks and receiver input pins (ac coupled). fpga functional description stratix gx devices contain a two-dimensional row- and column-based architecture to implement custom logic. a series of column and row interconnects of varying length and speed provide signal interconnects between logic array bloc ks (labs), memory block structures, and dsp blocks. lvds, lvpecl, 3.3-v pcml, and hypertransport i/o block and regular i/o pins (3) i/o banks 3, 4, 9 & 10 support all single-ended i/o standards (2) i/o banks 7, 8, 11 & 12 support all single-ended i/o standards (2) i/o banks 1 and 2 support all single-ended i/o standards except differential hstl output clocks, differential sstl-2 output clocks, hstl class ii, gtl, sstl-18 class ii, pci, pci-x, and agp 1 /2 dqst9 dqst8 dqst7 dqst6 dqst5 dqst4 dqst3 dqst2 dqst1 dqst0 pll5 vref1b3 vref2b3 vref3b3 vref4b3 vref5b3 vref1b4 vref2b4 vref3b4 vref4b4 vref5b4 vref5b8 vref4b8 vref3b8 vref2b8 vref1b8 vref5b7 vref4b7 vref3b7 vref2b7 vref1b7 pll6 dqsb9 dqsb8 dqsb7 dqsb6 dqsb5 dqsb4 dqsb3 dqsb2 dqsb1 dqsb0 910 vref1b2 vref2b2 vref3b2 vref4b2 vref1b1 vref2b1 vref3b1 vref4b1 pll1 pll2 bank 1 bank 2 bank 3 bank 4 11 12 bank 8 bank 7 lvds, lvpecl, 3.3-v pcml, and hypertransport i/o block and regular i/o pins (3) pll7 pll8 pll12 pll11 (4) (4) i/o bank 13 (5) i/o bank 14 (5) i/o bank 17 (5) i/o bank 16 (5) i/o bank 15 (5) 1.5-v pcml (5)
1?6 altera corporation stratix gx device handbook, volume 1 february 2005 fpga functional description the logic array consists of labs, wi th 10 logic elements (les) in each lab. an le is a small unit of logic providing efficient implementation of user logic functions. labs are grouped into rows and columns across the device. m512 ram blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). these blocks prov ide dedicated simple dual-port or single-port memory up to 18-bits wide at up to 318 mhz. m512 blocks are grouped into columns across the device in between certain labs. m4k ram blocks are true dual-port me mory blocks with 4k bits plus parity (4,608 bits). these blocks provide dedicated true dual-port, simple dual-port, or single-por t memory up to 36-bits wide at up to 291 mhz. these blocks are grouped into columns across the device in between certain labs. m-ram blocks are true dual-port me mory blocks with 512k bits plus parity (589,824 bits). these blocks provide dedicated true dual-port, simple dual-port, or single-port me mory up to 144-bits wide at up to 269 mhz. several m-ram blocks are located individually or in pairs within the device?s logic array. digital signal processing (dsp) blocks can implem ent up to either eight full-precision 9 9-bit multipliers, four full-precision 18 18-bit multipliers, or one full -precision 36 36-bit mul tiplier with add or subtract features. these blocks also contain 18-bit input shift registers for digital signal processing applications, including fir and infinite impulse response (iir) filters. dsp blocks are grouped into two columns in each device. each stratix gx device i/o pin is fed by an i/o element (ioe) located at the end of lab rows and columns ar ound the periphery of the device. i/o pins support numerous single-end ed and differential i/o standards. each ioe contains a bidirectional i/o buffer and six registers for registering input, output, and output -enable signals. when used with dedicated clocks, these registers provide exceptional performance and interface support with external memory devi ces such as ddr sdram, fcram, zbt, and qdr sram devices. high-speed serial interface channels support transfers at up to 840 mbps using lvds, lvpecl, 3.3-v pcml, or hypertransport technology i/o standards. figure 1?2 shows an overview of the stratix gx device.
altera corporation 1?7 february 2005 stratix gx device handbook, volume 1 introduction to the stratix gx device data sheet figure 1?2. stratix gx block diagram the number of m512 ram, m4k ram, and dsp blocks varies by device along with row and column numbers and m-ram blocks. table 1?5 lists the resources available in stratix gx devices. m512 ram blocks for dual-port memory, shift registers, & fifo buffers dsp blocks for multiplication and full implementation of fir filters m4k ram blocks for true dual-port memory & other embedded memory functions ioes support ddr, pci, gtl+, sstl-3, sstl-2, hstl, lvds, lvpecl, pcml, hypertransport & other i/o standards ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes labs labs ioes labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs ioes labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs ioes ioes labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs dsp block m-ram block table 1?5. stratix gx device resources device m512 ram columns/blocks m4k ram columns/blocks m-ram blocks dsp block columns/blocks lab columns lab rows ep1sgx10 4 / 94 2 / 60 1 2 / 6 40 30 ep1sgx25 6 / 224 3 / 138 2 2 / 10 62 46 ep1sgx40 8 / 384 3 / 183 4 2 / 14 77 61
1?8 altera corporation stratix gx device handbook, volume 1 february 2005 fpga functional description
altera corporation 2?1 june 2006 2. stratix gx transceivers transceiver blocks stratix ? gx devices incorporate dedicated embedded circuitry on the right side of the device, which cont ains up to 20 high-speed 3.1875-gbps serial transceiver channels. each st ratix gx transceiver block contains four full-duplex channels and supporting logic to transmit and receive high-speed serial data streams. the transceiver block uses the channels to deliver bidirectional point-to-poin t data transmissions with up to 3.1875 gbps of data transition per channel. there are up to 20 transceiver channe ls available on a single stratix gx device. table 2?1 shows the number of transc eiver channels available on each stratix gx device. figure 2?1 shows the elements of the transc eiver block, including the four channels, supporting logic, and i/o buffers. each transceiver channel consists of a receiver and transmit ter. the supporting logic contains a transmitter pll to generate a high -speed clock used by the four transmitters. the receiver pll within each transceiver channel generates the receiver reference clocks. the supporting logic also contains state machines to manage rate matching fo r xaui and gige applications, in addition to channel bonding for xaui applications. table 2?1. stratix gx transceiver channels device number of transceiver channels ep1sgx10c 4 ep1sgx10d 8 ep1sgx25c 4 ep1sgx25d 8 ep1sgx25f 16 ep1sgx40d 8 ep1sgx40g 20 sgx51002-1.1
2?2 altera corporation stratix gx device handbook, volume 1 june 2006 figure 2?1. stratix gx transceiver block note (1) notes to figure 2?1 : (1) each receiver channel has its own pll and cru, which are not shown in this diagram. for more information, refer to the section ?receiver path? on page 2?13 . (2) for possible transmit ter pll clock inputs, refer to the section ?transmitter path? on page 2?5 . channel 0 receiver channel 0 transmitter channel 0 receiver pins transmitter pins channel 1 receiver channel 1 transmitter channel 1 receiver pins transmitter pins xaui receiver state machine transmitter pll xaui transmitter state machine channel aligner state machine receiver pins transmitter pins receiver pins transmitter pins pld logic array pld logic array pld logic array pld logic array pld logic array pld logic array channel 2 receiver channel 2 transmitter channel 2 channel 3 receiver channel 3 transmitter channel 3 ( 2 )
altera corporation 2?3 june 2006 stratix gx device handbook, volume 1 stratix gx transceivers each stratix gx transceiver channel cons ists of a transmitter and receiver. the transmitter contains the following: transmitter pll transmitter phase compensation fifo buffer byte serializer 8b/10b encoder serializer (parallel to serial converter) transmitter output buffer the receiver contains the following: input buffer clock recovery unit (cru) deserializer pattern detector and word aligner rate matcher and channel aligner 8b/10b decoder receiver logic array interface you can set all the stratix gx transcei ver functions thro ugh the quartus ii software. you can set programmabl e pre-emphasis, programmable equalizer, and programmable v od dynamically as well. each stratix gx transceiver channel is also capable of bist generation and verification in addition to various loopback modes. figure 2?2 shows the block diagram for the stratix gx transceiver channel. stratix gx transceivers provide phys ical coding sublayer (pcs) and physical media attachment (pma) impl ementation for protocols such as 10-gigabit xaui and gige. the pcs port ion of the transceiver consists of the logic array interface, 8b/10b encoder/decoder, pattern detector, word aligner, rate matcher, channel alig ner, and the bist and pseudo-random binary sequence pattern generator/ verifier. the pma portion of the transceiver consists of the serializ er/deserializer, the cru, and the i/o buffers.
2?4 altera corporation stratix gx device handbook, volume 1 june 2006 figure 2?2. stratix gx transceiver channel note (1) note to figure 2?2 : (1) there are four transceiver channels in a transceiver block. deserializer serializer receiver pll transmitter pll clock recovery unit word aligner channel aligner rate matcher 8b/10b decoder byte deserializer phase compensation fifo 8b/10b encoder byte serializer receiver reference clock phase compensation fifo receiver transmitter channel 0 to channels 1-3 transmitter reference clock
altera corporation 2?5 june 2006 stratix gx device handbook, volume 1 stratix gx transceivers transmitter path this section describes the data path through the stratix gx transmitter (see figure 2?2 ). data travels through the stratix gx transmitter via the following modules: transmitter pll transmitter phase compensation fifo buffer byte serializer 8b/10b encoder serializer (parallel to serial converter) transmitter output buffer transmitter pll each transceiver block has one tran smitter pll, which receives the reference clock and genera tes the following signals: high-speed serial clock used by the serializer slow-speed reference clock used by the receiver slow-speed clock used by the lo gic array (divisible by two for double-width mode) the inclk clock is the input into the transmitter pll. there is one inclk clock per transceiver block. this clock can be fed by either the refclkb pin, pld routing, or the inter-tran sceiver routing line. see the section ?stratix gx clocking? on page 2?30 for more information about the inter- transceiver lines. the transmitter pll in each transceive r block clocks the circuits in the transmit path. the transmitter pll is al so used to train the receiver pll. if no transmit channels are used in the transceiver block, the transmitter pll can be turned off. figure 2?3 is a block diagram of the transmitter pll.
2?6 altera corporation stratix gx device handbook, volume 1 june 2006 figure 2?3. transmitter pll block diagram note (1) note to figure 2?3 : (1) the divider in the pll divides by 4, 8, 10, 16, or 20. inter quad routing (iq1) inter quad routing (iq0) global clks, io bus, gen routing dedicated local refclkb 2 inclk charge pump + loop filter clock driver m up down high speed cloc k low speed clock vco pfd
altera corporation 2?7 june 2006 stratix gx device handbook, volume 1 stratix gx transceivers the transmitter pll can support up to 3.1875 mbps. the input clock frequency for ?5 and ?6 speed grade devices is limited to 650 mhz if you use the refclkb pin or to 325 mhz if you use the other clock routing resources. for ?7 speed grade devices, the maximum input clock frequency is 312.5 mhz with the refclkb pin, and the maximum is 156.25 mhz for all other clock routing resources. an optional pll_locked port is available to indicate whether the transmitter pll is locked to the reference clock. the transmitter pll has a programmable loop bandwidth that can be set to low or high. the loop bandwidth parameter can be statically set in the quartus ii software. table 2?2 lists the adjustable parameters in the transmitter pll. transmitter phase compensation fifo buffer the transmitter phase compensation fifo buffer resides in the transceiver block at the pld boundary . this fifo buffer compensates for the phase differences between th e transmitter reference clock ( inclk ) and the pld interface clock ( tx_coreclk ). the phase difference between the two clocks must be less than 360 . the pld interface clock must also be frequency locked to th e transmitter reference clock. the phase compensation fifo buffer is four words deep and cannot be bypassed. byte serializer the byte serializer takes double-width words (16 or 20 bits) from the pld interface and converts them to a single width word (8 or 10 bits) for use in the transceiver. the transmit data pa th after the byte serializer is single width (8 or 10 bits). the byte serial izer is bypassed when single width mode (8 or 10 bits) is us ed at the pld interface. table 2?2. transmitter pll specifications parameter specifications input reference frequency range 25 mhz to 650 mhz data rate support 500 mbps to 3.1875 gbps multiplication factor (w) 2, 4, 5, 8, 10, 16, or 20 (1) bandwidth low, high note to ta b l e 2 ? 2 : (1) multiplication factors 2 and 5 can only be achieved with the use of the pre-divider on the refclkb pin.
2?8 altera corporation stratix gx device handbook, volume 1 june 2006 8b/10b encoder the 8b/10b encoder translates 8-bit wide data + 1 control enable bit into a 10-bit encoded data. the encoded data has a maximum run length of 5. the 8b/10b encoder can be bypassed. figure 2?4 diagrams the encoding process. figure 2?4. encoding process transmit state machine the transmit state machine operates in either xaui mode or in gige mode, depending on the protocol used. gige mode in gige mode, the transmit state machines convert all idle ordered sets ( /k28.5/ , /dx.y/ ) to either /i1/ or /i2/ ordered sets. /i1/ consists of a negative-ending disparity /k28.5/ (denoted by /k28.5/- ) followed by a neutral /d5.6/ . /i2/ consists of a positive-ending disparity /k28.5/ (denoted by /k28.5/+ ) and a negative-ending disparity /d16.2/ (denoted by /d16.2/- ). the transmit state machines do not convert any of the ordered sets to match /c1/ or /c2/ , which are the configuration ordered sets. ( /c1/ and /c2/ are defined by ( /k28.5/ , /d21.5/ ) and ( /k28.5/ , /d2.2/ ), respectively.) both the /i1/ and /i2/ ordered sets guarantee a negative-ending disparity after each ordered set. the gige transmit state machine can be statically disabled in the quartus ii software , even if using the gige protocol mode. 9876543210 8b-10b conversion 76543210 hgfed cb a + ctrl jhgfiedcba msb sent last lsb sent firs t
altera corporation 2?9 june 2006 stratix gx device handbook, volume 1 stratix gx transceivers xaui mode the transmit state machine translates the xaui xgmii code group to the xaui pcs code group. table 2?3 shows the code conversion. the xaui pcs idle code groups, /k28.0/ ( /r/ ) and /k28.5/ ( /k/ ), are automatically randomiz ed based on a prbs7 pattern with an x 7 +x 6 +1 polynomial. the /k28.3/ ( /a/ ) code group is automatically generated between 16 and 31 idle code groups. the idle randomization on the /a/ , /k/ , and /r/ code groups are done automat ically by the transmit state machine. serializer (parallel-to-serial converter) the serializer converts the parallel 8-bi t or 10-bit data into a serial stream, transmitting the lsb first. the serialized stream is then fed to the transmit buffer. figure 2?5 is a diagram of the serializer. table 2?3. code conversion xgmii txc xgmii txd pcs code-group description 0 00 through ff dxx.y normal data 1 07 k28.0 or k28.3 or k28.5 idle in || i || 1 07 k28.5 idle in || t || 1 9c k28.4 sequence 1 fb k27.7 start 1 fd k29.7 terminate 1 fe k30.7 error 1 see ieee 802.3 reserved code groups see ieee 802.3 reserved code groups reserved code groups 1 other value k30.7 invalid xgmii character
2?10 altera corporation stratix gx device handbook, volume 1 june 2006 figure 2?5. serializer transmit buffer the stratix gx transceiver buffers support the 1.5-v pseudo current mode logic (pcml) i/o standard at a rate up to 3.1875 gbps, across up to 40 inches of fr4 trace, and across 2 connectors. addition al i/o standards, lvds, 3.3-v pcml, lvpecl, can be supported when ac coupled. the common mode of the output driver is 750 mv. the output buffer, as shown in figure 2?6 , consists of a programmable output driver and a programmable pre-emphasis circuit. d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 low-speed parallel clock hi g h-speed serial clock serial data out (to output buffer) d8 d9 d8 d9 10
altera corporation 2?11 june 2006 stratix gx device handbook, volume 1 stratix gx transceivers figure 2?6. output buffer programmable output driver the programmable output driver can be set to drive out 400 to 1,600 mv. table 2?4 shows the available settings for each termination value. the v od can be dynamically or statically set. the output driver requires either internal or external termination at the source. table 2?4. programmable v od (differential) note (1) termination setting ( ) v od setting (mv) 100 400, 800, 1000, 1200, 1400, 1600 120 480, 960, 1200, 1440 150 600, 1200, 1500 note to ta b l e 2 ? 4 : (1) v od differential is measured as v a ? v b (see figure 2?7 ). serializer pro g rammable termination pro g rammable pre-emphasis output buffer output pins pro g rammable output driver
2?12 altera corporation stratix gx device handbook, volume 1 june 2006 figure 2?7. v od differential programmable pre-emphasis the programmable pre-emphasis module controls the output driver to boost the high frequency components , to compensate for losses in the transmission medium, as shown in figure 2?8 . the pre-emphasis can be dynamically or statically set. there are five possible pre-emphasis settings (1 through 5), with 5 being the highest and 0 being no pre-emphasis. figure 2?8. programmable pre-emphasis model single-ended waveform differential waveform (v id (differential) = 2 x v id (single-ended)) positive channel (p) = v oh negative channel (n) = v ol ground v id v id v id p ? n = 0 v v cm v cm v pp (p-p) v s (p-p) bit time v pp bit time v s
altera corporation 2?13 june 2006 stratix gx device handbook, volume 1 stratix gx transceivers pre-emphasis percentage is defined as v pp /v s ? 1, where v pp is the differential emphasized vo ltage (peak-to-peak) and v s is the differential steady-state voltage (peak-to-peak). programmable transmitter termination the programmable termination can be statically set in the quartus ii software. the values are 100 , 120 , 150 , and off. figure 2?9 shows the setup for programmable termination. figure 2?9. programmable transmitter termination receiver path this section describes the data path through the stratix gx receiver (refer to figure 2?2 on page 2?4 ). data travels through the stratix gx receiver via the following modules: input buffer clock recovery unit (cru) deserializer pattern detector and word aligner rate matcher and channel aligner 8b/10b decoder receiver logic array interface receiver input buffer the stratix gx receiver input buff er supports the 1.5-v pcml i/o standard at a rate up to 3.1875 gbps . additional i/o standards, lvds, 3.3-v pcml, and lvpecl can be supported when ac coupled. the common mode of the input buffer is 1.1 v. the receiver can support stratix gx-to-stratix gx dc coupling. programmable output driver 50, 60, or 75 v cm
2?14 altera corporation stratix gx device handbook, volume 1 june 2006 figure 2?10 shows a diagram of the receiver input buffer, which contains: programmable termination programmable equalizer figure 2?10. receiver input buffer programmable termination the programmable termination can be statically set in the quartus ii software. figure 2?11 shows the setup for programmable receiver termination. figure 2?11. programmable receiver termination if you use external termination, then the receiver must be externally terminated and biased to 1.1 v. figure 2?12 shows an example of an external terminatio n/biasing circuit. programmable termination input pins differential input buffer programmable equalizer differential input buffer 50, 60, or 75 50, 60, or 75 v cm
altera corporation 2?15 june 2006 stratix gx device handbook, volume 1 stratix gx transceivers figure 2?12. external termi nation & biasing circuit programmable equalizer the programmable equalizer module boosts the high frequency components of the incomi ng signal to compensate for losses in the transmission medium. there are five possible equalization settings (0, 1, 2, 3, 4) to compensate for 0?, 10?, 20?, 30?, and 40? of fr4 trace. these settings should be interpreted loosel y. the programmable equalizer can be set dynamically or statically. receiver pll & cru each transceiver block has four receiver plls and crus, each of which is dedicated to a receive channel. if the receive channel associated with a particular receiver pll or cru is n ot used, then the re ceiver pll or cru is powered down for the channel. figure 2?13 is a diagram of the receiver pll and cru circuits. transmission line c1 r1/r2 = 1k v dd {r2/(r1 + r 2)} = 1.1 v 50/60/75- termination resistance r1 r2 v dd receiver external termination and biasing stratix gx device receiver external termination and biasing rxip rxin receiver
2?16 altera corporation stratix gx device handbook, volume 1 june 2006 figure 2?13. receiver pll & cru circuit note to figure 2?13 : (1) m = 8, 10 16, or 20. the receiver plls and crus are ca pable of supporting up to 3.1875 gbps. the input clock frequency for ?5 and ?6 speed grade devices is limited to 650 mhz if you use the refclkb pin or 325 mhz if you use the other clock routing resources. the maximum input clock frequency for ?7 speed grade devices is 312.5 mhz if you use the refclkb pin or 156.25 mhz with the other clock routin g resources. an optional rx_locked port (active low signal) is available to indicate whether the pll is locked to the reference clock. the receiver pll has a programmable loop bandwidth, which can be set to low, medium, or high. the loop bandwidth parameter can be statically set by the quartus ii software. table 2?5 lists the adjustable parameters of the receiver pll and cru. all the parameters listed are statical ly programmable in the quartus ii software. dedicated local refclkb 2 pfd vco m (1) charge pump and loop filter rx_riv[ ] cru global clks, io bus, gen routing rx_locktorefclk rx_locktodata rx_in rx_freqlocked[] high-speed rcvd_clk low-speed rcvd_clk low-speed tx_pll_clk rx cruclk up down up down receiver pll inter transceiver routing (iq2) rx_locked table 2?5. receiver pll & cru adjustable parameters (part 1 of 2) parameter specifications input reference frequency range 25 mhz to 650 mhz data rate support 500 mbps to 3.1875 gbps
altera corporation 2?17 june 2006 stratix gx device handbook, volume 1 stratix gx transceivers the cru has a built-in switchover circuit to select whether the voltage-controlled oscillator of the pl l is trained by the reference clock or the data. the optional port rx_freqlocked monitors when the cru is in locked to data mode. in the automatic mode, the following conditions must be met for the cru to switch from locked to refe rence to locked to data mode: the cru pll is within the prescribed ppm frequency threshold setting (125 ppm, 250 ppm, 500 ppm, 1,000 ppm) of the cru reference clock. the reference clock and cru pll output are phase matched (phases are within .08 ui). the automatic switchover circuit can be overridden by using the optional ports rx_lockedtorefclk and rx_locktodata . table 2?6 shows the possible combinations of these two signals. if the rx_lockedtorefclk and rx_locktodata ports are not used, the default is auto mode. multiplication factor (w) 2, 4, 5, 8, 10, 16, or 20 (1) ppm detector 125, 250, 500, 1,000 bandwidth low, medium, high run length detector 10-bit or 20-bit mode: 5 to 160 in steps of 5 8-bit or 16-bit mode: 4 to 128 in steps of 4 note to ta b l e 2 ? 5 : (1) multiplication factors 2, 4, and 5 can only be achieved with the use of the pre- divider on the refclkb port or if the cru is trained with the low speed clock from the transmitter pll. table 2?6. possible combinations of rx_lockedtorefclk & rx_locktodata rx_locktodata rx_lockedtorefclk vco (lock to mode) 00auto 0 1 reference clk 1xdata table 2?5. receiver pll & cru adjustable parameters (part 2 of 2)
2?18 altera corporation stratix gx device handbook, volume 1 june 2006 deserializer (serial-to-parallel converter) the deserializer converts the serial st ream into a parallel 8- or 10-bit data bus. the deserializer receives the least significant bit first. figure 2?14 is a diagram of the deserializer. figure 2?14. deserializer word aligner the word aligner aligns the incoming data based on the specific byte boundaries. the word aligner has thre e customizable modes of operation: bit-slip mode, 16-bit mode, and 10-bit mo de, the last of which is available for the basic and sonet modes. the word aligner also has two non-customizable modes of operatio n, which are the xaui and gige modes. figure 2?15 shows the word aligne r in bit-slip mode. hi g h-speed serial clock d7 d6 d5 d4 d3 d2 d1 d0 d8 d9 low-speed parallel clock d7 d6 d5 d4 d3 d2 d1 d0 d8 d9 10
altera corporation 2?19 june 2006 stratix gx device handbook, volume 1 stratix gx transceivers figure 2?15. word aligner in bit-slip mode in the bit-slip mode, the byte boundary can be modified by a barrel shifter to slip the byte boundary one bit at a time via a user-controlled bit-slip port. the bit-slip mode supports both 8-bit and 10-bit data paths operating in a single or double-width mode. the pattern detector is active in th e bit-slip mode, and it detects the user-defined pattern that is specified in the megawizard ? plug-in manager. the bit-slip mode is available only in custom mode and sonet mode. figure 2?16 shows the word aligner in 16-bit mode. word aligner patterm detector 10-bit mode 16-bit mode 7-bit mode a1a2 mode a1a1a2a2 mode bit-slip mode manual alignment mode
2?20 altera corporation stratix gx device handbook, volume 1 june 2006 figure 2?16. word aligner in 16-bit mode in the 16-bit mode, the word aligner and pattern detector automatically aligns and detects a user-defined 16-bit alignment pattern. this pattern can be in the format of a1a2 or a1a1a2a2 (for the sonet protocol). the re-alignment of the byte boundary ca n be done via a user-controlled port. the 16-bit mode supports only the 8-bi t data path in a single-width or double-width mode. the 16-bit mode is available only for the custom mode and sonet mode. the a1a1a2a2 word alignment pattern option is available only for the sonet mode and cannot be used in the custom mode. figure 2?17 shows the word aligner in 10-bit mode. word aligner pattern detector 16-bit mode a1a2 mode a1a1a2a2 mode manual alignment mode 16-bit mode a1a2 mode a1a1a2a2 mode
altera corporation 2?21 june 2006 stratix gx device handbook, volume 1 stratix gx transceivers figure 2?17. word aligner in 10-bit mode in the 10-bit mode, the word aligne r automatically al igns the user?s predefined 10-bit alignment pattern. th e pattern detector can detect the full 10-bit pattern or only the lower seven bits of the pattern. the word aligner and pattern detector detect both the positive and the negative disparity of the pattern. a user-control led enable port is available for the word aligner. the 10-bit mode is available only for the custom mode. figure 2?18 shows the word aligner in xaui mode. word aligner pattern detector 10-bit mode 7-bit mode manual alignment mode 10-bit mode
2?22 altera corporation stratix gx device handbook, volume 1 june 2006 figure 2?18. word aligner in xaui mode in the xaui and gige modes, the word alignment is controlled by a state machine that adheres to the ieee 802. 3ae standard for xaui and the ieee 802.3 standard for gige. the alignm ent pattern is predefined to be a /k28.5/ code group. the xaui mode is available only fo r the xaui protocol, and the gige mode is available only for the gige protocol. channel aligner the channel aligner is available only in xaui mode and bonds all four channels within a transceiver. the channel aligner adheres to the ieee 802.3ae, clause 48 specif ication for channel bonding. the channel aligner is a 16-word deep fifo buffer with a state machine overlooking the channel bonding proces s. the state machine looks for an /a/ ( /k28.3/ ) in each channel and aligns all the /a/ s in the transceiver. when four columns of /a/ (denoted by //a// ) are detected, the rx_channelalign port goes high, signifying that all the channels in the transceiver have been bonded. the reception of four consecutive misaligned /a/ s restarts the channel alignm ent sequence and de-asserts rx_channelalign . figure 2?19 shows misaligned channels before the channel aligner and the channel alignment after the channel aligner. word aligner synchronization state machines xaui mode gige mode
altera corporation 2?23 june 2006 stratix gx device handbook, volume 1 stratix gx transceivers figure 2?19. before & after the channel aligner rate matcher the rate matcher, which is available only in xaui and gige modes, consists of a 12-word deep fifo buffer and a fifo controller. the rate matcher is bypassed when the device is not in xaui or gige mode. in a multi-crystal environment, the rate matcher compensates for up to a 100-ppm difference between the source and receiver clocks. gige mode in the gige mode, the rate matche r adheres to the specifications in clause 36 of the ieee 802.3 documentation, for idle additio ns or removals. the rate matcher performs cl ock compensation only on /i2/ ordered sets, composing a /k28.5/+ followed by a /d16.2/- . the rate matcher does not perform a clock compensa tion on any other ordered set combinations. an /i2/ is added or deleted automatically based on the number of words in the fifo buffer. a 9?h19c is given at the control and data ports when the fifo is in an overflow or underflow condition. kr kkk r r rkk r a lane 0 kr kkk r r rkk r a lane 0 kr kkk r r rkk r a lane 0 kr kkk r r rkk r a lane 0 kr kkk r r rkk r a lane 0 kr kkk r r rkk r a lane 0 kr kkk r r rkk r a lane 0 kr kkk r r rkk r a lane 0
2?24 altera corporation stratix gx device handbook, volume 1 june 2006 xaui mode in xaui mode, the rate matcher adheres to clause 48 of the ieee 802.3ae specification for clock rate compensation. the rate matcher performs clock compensation on columns of /r/ ( /k28.0/ ), denoted by //r// . an //r// is added or deleted automatically based on the number of words in the fifo buffer. 8b/10b decoder the 8b/10b decoder converts the 10-bit encoded code group into 8-bit data and 1 control bit. the 8b/10b decoder can be bypassed. the following is a diagram of the conv ersion from a 10-bit encoded code group into 8-bit data + 1-bit control. figure 2?20. 8b/10b de coder conversion there are two optional error status po rts available in the 8b/10b decoder, rx_errdetect and rx_disperr . table 2?7 shows the values of the ports from a given error. these status signals are aligned with the code group in which the error occurred. table 2?7. error signal values types of errors rx_errdetect rx_disperr no errors 1?b0 1?b0 invalid code groups 1?b1 1?b0 disparity errors 1?b1 1?b1 9876543210 8b-10b conversion jhgfiedcba msb received last lsb received first 76543210 hgfed cb a + ctrl parallel data
altera corporation 2?25 june 2006 stratix gx device handbook, volume 1 stratix gx transceivers receiver state machine the receiver state machine operates in gige and xaui modes. in gige mode, the receiver state machine replaces invalid code groups with 9?h1fe . in xaui mode, the receiver st ate machine translates the xaui pcs code group to the xa ui xgmii code group. table 2?8 shows the code conversion. the conversi on adheres to the ieee 802.3ae specification. byte deserializer the byte deserializer takes a single width word (8 or 10 bits) from the transceiver logic and converts it into double-width words (16 or 20 bits) to the phase compensation fifo buffer . the byte deserializer is bypassed when single width mode (8 or 10 bits) is used at the pld interface. phase compensation fifo buffer the receiver phase compensation fifo buffer resides in the transceiver block at the programmable logic de vice (pld) bounda ry. this buffer compensates for the phase difference between the recovered clock within the transceiver and the recovered cloc k after it has transferred to the pld core. the phase compensation fifo buffer is four words deep and cannot be bypassed. table 2?8. code conversion xgmii rxc xgmii rxd pcs code-group description 0 00 through ff dxx.y normal data 1 07 k28.0 or k28.3 or k28.5 idle in || i || 1 07 k28.5 idle in || t || 1 9c k28.4 sequence 1 fb k27.7 start 1 fd k29.7 terminate 1fe k30.7 error 1 fe invalid code group invalid xgmii character 1 see ieee 802.3 reserved code groups see ieee 802.3 reserved code groups reserved code groups
2?26 altera corporation stratix gx device handbook, volume 1 june 2006 loopback modes the stratix gx transceiver has built-in loopback modes to aid in debug and testing. the loopback modes are set in the stratix gx megawizard plug-in manager in the quartus ii software. only one loopback mode can be set at any single instance of the transceiver block. the loopback mode applies to all used channe ls in a transceiver block. the available loopback modes are: serial loopback parallel loopback reverse serial loopback serial loopback serial loopback exercises all the tran sceiver logic except for the output buffer and input buffer. the loopback function is dynamically switchable through the rx_slpbk port on a channel by channel basis. the v od of the output reduced. if you select 400 mv, the output is tri-stated when the serial loopback option is selected. figure 2?21 shows the data path in serial loopback mode. figure 2?21. data path in serial loopback mode non-active path active path clock recovery unit bist prbs verifier bist incremental verifier channel aligner rate matcher 8b/10b decoder byte deserializer phase compensation fifo byte serializer serializer bist prbs generator 8b/10b encoder deserializer word aligner phase compensation fifo bist generator
altera corporation 2?27 june 2006 stratix gx device handbook, volume 1 stratix gx transceivers parallel loopback the parallel loopback mode exercises the digital logic portion of the transceiver data path. the analog po rtions are not use in the loopback path. the received data is not retimed. figure 2?22 shows the data path in parallel loopback mode. this opti on is not dynamically switchable. reception of an external signal is not possible in this mode. figure 2?22. data path in parallel loopback mode reverse serial loopback the reverse serial loopback exer cises the analog portion of the transceiver. this loopback mode is dynamically switchable through the tx_srlpbk port on a channel by channel basis. asserting rxanalogreset in reverse serial loopba ck mode powers down the receiver buffer and cru, preventing data loopback. figure 2?23 shows the data path in reverse serial loopback mode. clock recovery unit word aligner bist prbs verifier bist incremental verifier channel aligner rate matcher bist generator byte deserializer phase compensation fifo phase compensation fifo byte serializer serializer bist prbs generator 8b/10b encoder 8b/10b decoder deserializer non-active path active path
2?28 altera corporation stratix gx device handbook, volume 1 june 2006 figure 2?23. data path in reverse serial loopback mode bist (built-in self test) the stratix gx transceiver has built-in self test modes to aid in debug and testing. the bist modes are set in the stratix gx megawizard plug-in manager in the quartus ii software. only one bist mode can be set for any single instance of th e transceiver block. the bist mode applies to all channels used in a transceiver. the following is a list of the available bist modes: prbs generator and verifier incremental mode generator and verifier high-frequency generator low-frequency generator mixed-frequency generator figures 2?24 and 2?25 are diagrams of the bist prbs data path and the bist incremental data path, respectively. non-active path active path clock recovery unit deserializer bist prbs verifier bist incremental verifier bist generator byte deserializer phase compensation fifo byte serializer bist prbs generator 8b/10b encoder serializer phase compensation fifo 8b/10b decoder rate matcher channel aligner word aligner
altera corporation 2?29 june 2006 stratix gx device handbook, volume 1 stratix gx transceivers figure 2?24. bist prbs data path figure 2?25. bist incremental data path table 2?9 shows the bist data output and verifier alignment pattern. clock recovery unit deserializer word aligner bist prbs verifier bist incremental verifier bist generator byte deserializer phase compensation fifo phase compensation fifo byte serializer channel aligner rate matcher 8b/10b decoder serializer bist prbs generator 8b/10b encoder non-active path active path deserializer word aligner bist prbs verifier channel aligner rate matcher 8b/10b decoder bist generator byte deserializer phase compensation fifo serializer bist prbs generator 8b/10b encoder non-active path active path clock recovery unit bist incremental verifier phase compensation fifo byte serializer table 2?9. bist data output & verifier alignment pattern (part 1 of 2) bist mode output polynomials veri fier word alignment pattern prbs 8-bit 2 8 ? 1 x 8 + x 7 + x 5 + x 3 + 1 1000000011111111 prbs 10-bit 2 10 ? 1 x 10 + x 7 + 1 1111111111
2?30 altera corporation stratix gx device handbook, volume 1 june 2006 stratix gx clocking the stratix gx global clock can be driven by certain refclkb pins, all transmitter pll outputs, and al l receiver pll outputs. the refclkb pins (except for transceiver block 0 and tr ansceiver block 4) can drive inter- transceiver and global cl ock lines as well as feed the transmitter and receiver plls. the output of the tr ansmitter pll can only feed global clock lines and the reference cl ock port of the receiver pll. figures 2?26 and 2?27 are diagrams of the inter-transceiver line connections as well as the global clock connections for the ep1sgx25f and ep1sgx40g devices. for devices wi th fewer transceivers, ignore the information about the unavai lable transceiver blocks. prbs 16-bit 2 8 ? 1 x 8 + x 7 + x 5 + x 3 + 1 1000000011111111 prbs 20-bit 2 10 ? 1 x 10 + x 7 + 1 1111111111 incremental 10-bit k28.5, k27.7, data (00-ff incremental), k28.0, k28.1, k28.2, k28.3, k28.4, k28.6, k28.7, k23.7, k30.7, k29.7 (1) 0101111100 (k28.5) incremental 20-bit k28.5, k27.7, data (00-ff incremental), k28.0, k28.1, k28.2, k28.3, k28.4, k28.6, k28.7, k23.7, k30.7, k29.7 (1) 0101111100 (k28.5) high frequency 1010101010 low frequency 0011111000 mixed frequency 0011111010 or 1100000101 note to ta b l e 2 ? 9 : (1) this output repeats. table 2?9. bist data output & verifier alignment pattern (part 2 of 2) bist mode output polynomials veri fier word alignment pattern
altera corporation 2?31 june 2006 stratix gx device handbook, volume 1 stratix gx transceivers figure 2?26. ep1sgx25f device inter-trans ceiver & global clock connections note (1) notes to figure 2?26 : (1) iq lines are inter-transceiver block lines. (2) if the /2 pre-divider is used, the path to drive the pl d logic array, local, or global clocks is not allowed. (3) there are four receiver pl ls in each tr ansceiver block. 16 iq0 iq1 iq2 transceiver block 0 iq0 iq1 global clocks, i/o bus, general routing global clocks, i/o bus, general routing iq2 /2 4 4 receiver plls transmitter pll pld global clock s transceiver block 1 iq0 iq1 global clocks, i/o bus, general routing global clocks, i/o bus, general routing iq2 /2 4 4 receiver plls transmitter pll transceiver block 2 iq0 iq1 global clocks, i/o bus, general routing global clocks, i/o bus, general routing iq2 /2 4 4 receiver plls transmitter pll transceiver block 3 iq0 iq1 global clocks, i/o bus, general routing global clocks, i/o bus, general routing iq2 /2 4 4 receiver plls transmitter pll refclkb refclkb refclkb refclkb ( 2 ) ( 2 ) ( 2 )
2?32 altera corporation stratix gx device handbook, volume 1 june 2006 figure 2?27. ep1sgx40g device inter-tr ansceiver & global clock connections note (1) notes to figure 2?27 : (1) iq lines are inter-transceiver block lines. (2) if the /2 pre-divider is used, the path to drive the pl d logic array, local, or global clocks is not allowed. (3) there are four receiver pl ls in each tr ansceiver block. pld global clocks iq0 iq1 iq2 16 transceiver block 2 tx pll iq0 iq1 global clks, i/o bus, gen routing global clks, i/o bus, gen routing iq2 transceiver block 3 tx pll iq0 iq1 global clks, i/o bus, gen routing global clks, i/o bus, gen routing iq2 /2 tx pll iq0 iq1 global clks, i/o bus, gen routing global clks, i/o bus, gen routing iq2 transceiver block 0 transceiver block 1 tx pll iq0 iq1 global clks, i/o bus, gen routing global clks, i/o bus, gen routing iq2 tx pll iq0 iq1 global clks, i/o bus, gen routing global clks, i/o bus, gen routing iq2 transceiver block 4 /2 /2 /2 4 4 4 4 4 4 receiver plls 4 receiver plls 4 receiver plls 4 receiver plls refclkb refclkb refclkb refclkb refclkb /2 4 receiver plls (2) (2) (2)
altera corporation 2?33 june 2006 stratix gx device handbook, volume 1 stratix gx transceivers the receiver pll can also drive the fast regional, regional clocks, and local routing adjacent to the associated transceiver block. figures 2?28 through 2?31 show which fast regional and regional clock resource can be used by the recovered clock. in the ep1sgx25 device, the receiver pll recovered clocks from transceiver blocks 0 and 1 drive rclk[1..0] while transceiver blocks 2 and 3 drive rclk[7..6] . the regional clocks feed logic in their associated regions. figure 2?28. ep1sgx25 receiver pll re covered clock to regional clock connection in addition, the receiver pll?s recovered clocks can drive fast regional lines ( fclk ) as shown figure 2?29 . the fast regional clocks can feed logic in their associated regions. stratix gx transceiver blocks pld rclk[11..10] block 0 block 1 block 2 block 3 rclk[9..8]
2?34 altera corporation stratix gx device handbook, volume 1 june 2006 figure 2?29. ep1sgx25 receiver pll reco vered clock to fast regional clock connection in the ep1sgx40 device, the receiver pll recovered clocks from transceivers 0 and 1 drive rclk[1..0] while transceivers 2, 3, and 4 drive rclk[7..6] . the regional clocks feed logic in their associated regions. pld fclk[1..0] fclk[1..0] block 0 block 1 block 2 block 3 stratix gx transceiver blocks
altera corporation 2?35 june 2006 stratix gx device handbook, volume 1 stratix gx transceivers figure 2?30. ep1sgx40 receiver pll re covered clock to regional clock connection figure 2?31 shows the possible recovered cl ock connection to the fast regional clock resource. the fast regional clocks can drive logic in their associated regions. pld stratix gx transceiver blocks block 0 block 1 block 4 block 2 block 3 rclk[9..8] rclk[11..10]
2?36 altera corporation stratix gx device handbook, volume 1 june 2006 figure 2?31. ep1sgx40 receiver pll reco vered clock to fast regional clock connection table 2?10 summarizes the possible clocking connections for the transceivers. pld fclk[1..0] fclk[1..0] stratix gx transceiver blocks block 0 block 1 block 4 block 2 block 3 table 2?10. possible clocking connecti ons for transceivers (part 1 of 2) source destination transmitter pll receiver pll gclk rclk fclk iq lines refclkb vvv (1) vv (1) transmitter pll vvvv receiver pll vvv gclk vv rclk vv fclk vv
altera corporation 2?37 june 2006 stratix gx device handbook, volume 1 stratix gx transceivers other transceiver features other important features of the st ratix gx transceivers are the power down and reset capabilities, the ex ternal voltage reference and bias circuitry, and hot swapping. individual power-down & rese t for the transmitter & receiver stratix gx transceivers offer a power saving advantage with their ability to shut off functions that are not needed. the device can individually reset the receiver and transmitter blocks and the plls. the stratix gx device can either globally power down and reset the transmitter and receiver channels or do each channel separately. table 2?11 shows the connectivity between the reset signal s and the stratix gx logical blocks. iq lines v (2) v (2) notes to table 2?10 : (1) refclkb from transceiver block 0 and transceiver block 4 does not drive the inter-transceiver lines or the gclk lines. (2) inter-transceiver line 0 and inter-transc eiver line 1 drive the transmitter pll, while inter-transcei ver line 2 drives the receiver plls. table 2?10. possible clocking connecti ons for transceivers (part 2 of 2) source destination transmitter pll receiver pll gclk rclk fclk iq lines
2?38 altera corporation stratix gx device handbook, volume 1 june 2006 other transceiver features power-down functions are static, in other words., they are implemented upon device configuration and programmed, through the quartus ii software, to static values. resets can be static as well as dynamic inputs coming from the lo gic array or pins. voltage reference capabilities stratix gx transceivers provide voltag e reference and bias circuitry. to set-up internal bias for controlling th e transmitter output drivers? voltage swing?as well as to provide voltag e/current biasing for other analog circuitry?use the internal bandgap volt age reference at 0.7 v. to provide bias for internal pull-up pmos resis tors for i/o termination at the serial interface of receiver and transmitte r channels (independent of power supply drift, process changes, or te mperature variation) an external resistor, which is connected to the external low voltage power supply, is table 2?11. reset signal map to stratix gx blocks reset signal transmitter phase com pensation fifo module/ byte serializer transmitter 8b/10b encoder transmitter serializer transmitter analog circuits transmitter pll transmitter xaui state machine transmitter analog circuits bist generators receiver deserializer receiver word aligner receiver deskew fifo module receiver rate matcher receiver 8b/10b decoder receiver phase comp fifo module/ byte deserializer receiver pll / cru receiver xaui state machine bist verifiers receiver analog circuits rxdigitalreset vvvvv vv rxanalogreset vvv txdigitalreset vv v v pll_areset vvvvvvvvvvvvvvvvvv pllenable vvvvvvvvvvvvvvvvvv
altera corporation 2?39 june 2006 stratix gx device handbook, volume 1 stratix gx transceivers accurately tracked by the internal bi as circuit. moreover, the reference voltage and internal resi stor bias current is generated and replicated to the analog circuitry in each channel. hot-socketing capabilities each stratix gx device is capable of hot-socketing. because stratix gx devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. signals can be driven into stratix gx devices before and during power-up without damaging the device. once op erating conditions are reached and the device is configured, stratix gx devices operate according to your specifications. this feature provides the stratix gx transceiver line card behavior, so you can insert it in to the system without powering the system down, offering more flexibility. applications & protocols supported with stratix gx devices each stratix gx transceiver block is de signed to operate at any serial bit rate from 500 mbps to 3.1875 gbps per channel. the wide, data rate range allows stratix gx transceivers to suppo rt a wide variety of standard and future protocols such as 10-gigabit ethernet xaui, infiniband, fibre channel, and serial rapidio. strati x gx devices are ideal for many high- speed communication applications such as high-speed backplanes, chip- to-chip bridges, and hi gh-speed serial communications standards support. stratix gx example application support stratix gx devices can be used for many applications, including: backplanes for traffic management and quality of service (qos) switch fabric applications for complete set for backplane and switch fabric transceivers chip-to-chip applications such as: 10 gigabit ethe rnet xaui to xgmii bridge, 10 gigabit ethern et xgmii to pos-phy4 bridge, pos-phy4 to npsi bridge, or npsi to backplane bridge
2?40 altera corporation stratix gx device handbook, volume 1 june 2006 applications & protocols supported with stratix gx devices high-speed serial bus protocols with wide, serial data rate range, stratix gx devices can support multiple, high-speed serial bus protocols. table 2?12 shows some of the protocols that stratix gx devices can support. table 2?12. high-speed serial bus protocols bus transfer protocol stratix gx (gbps) (supports up to 3.1875 gbps) sonet backplane 2.488 10 gigabit ethernet xaui 3.125 10 gigabit fibre channel 3.1875 infiniband 2.5 fibre channel (1g, 2g) 1.0625, 2.125 serial rapidio ? 1.25, 2.5, 3.125 pci express 2.5 smpte 292m 1.485
altera corporation 3?1 august 2005 3. source-synchronous signaling with dpa introduction expansion in the telecommunications ma rket and growth in internet use requires systems to move more data faster than ever. to meet this demand, rely on solutions such as differential signaling and emerging high-speed interface standards including rapidio, pos-phy 4, sfi-4, or xsbi. these new protocols support differen tial data rates up to 1 gbps and higher. at these high data rates, it becomes more challenging to manage the skew between the clock and data signals. one solution to this challenge is to use cdr to eliminat e skew between data channels and clock signals. another potential so lution, dpa, is beginning to be incorporated into some of these protocols. the source-synchronous high-speed interface in stratix gx devices is a dedicated circuit embedded into the pld allowing for high-speed communications. the high-speed source-synchronous differential i/o interfaces in stratix gx devices chapter of the stratix gx device handbook, volume 2 provides information on the hi gh-speed i/o standard features and functions of the stratix gx device. stratix gx i/o banks stratix gx devices contain 17 i/o bank s. i/o banks one and two support high-speed lvds, lvpecl, and 3.3-v pcml inputs and outputs. these two banks also incorporate an embe dded dynamic phase aligner within the source-synchronous interface (see figure 3?8 on page 3?10 ). the dynamic phase aligner corrects for th e phase difference between the clock and data lines caused by skew. the dynamic phase aligner operates automatically and continuously wi thout requiring a fixed training pattern, and allows the source-synchronous circuitry to capture data correctly regardless of the channel-to-clock skew. principles of serdes operation stratix gx devices support source-synchronous differential signaling up to 1 gbps in dpa mode, and up to 840 mbps in non-dpa mode. serial data is transmitted and received al ong with a low-frequency clock. the pll can multiply the incoming low-freq uency clock by a factor of 1 to 10. the serdes factor j can be 8 or 10 for the dpa mode, or 4, 7, 8, or 10 for all other modes. the serdes factor does not have to equal the clock sgx51003-1.1
3?2 altera corporation stratix gx device handbook, volume 1 august 2005 introduction multiplication value. the 1 and 2 operation is also possible by bypassing the serdes. the serdes dpa cannot support 1, 2 , or 4 natively. on the receiver side, the high-frequenc y clock generated by the pll shifts the serial data through a shift register (also called deserializer). the parallel data is clocked out to the logic array synchron ized with the low- frequency clock. on the transmitter si de, the parallel data from the logic array is first clocked into a parallel-in, serial-out shift register synchronized with the low-frequency clock and then tr ansmitted out by the output buffers. there are two dedicated fast plls each in ep1sgx10 to ep1sgx25 devices, and four in ep1sgx40 devices. these plls are used for the serdes operations as well as general-purpose use. stratix gx differential i/o recei ver operation (non-dpa mode) you can configure any of the stratix g x source synchronous differential input channels as a receiver channel (see figure 3?1 ). the differential receiver deserializes the incoming high-speed data. the input shift register continuously clocks the incomi ng data on the negative transition of the high-frequency clock ge nerated by the pll clock ( w ). the data in the serial shift register is shifted into a parallel register by the rxloaden signal generated by the fast pll counter circuitry on the third falling edge of the high-frequency cl ock. however, you can select which falling edge of the high frequency clock loads the data into the parallel register, using the data-realignment circuit. in normal mode, the enable signal rxloaden loads the parallel data into the next parallel register on the second rising edge of the low-frequency clock. you can also load data to the parallel register through the txloaden signal when using the data-realignment circuit. figure 3?1 shows the block diagram of a single serdes receiver channel. figure 3?2 shows the timing relationship between the data and clocks in stratix gx devices in 10 mode. w is the low-frequency multiplier and j is the data paralleli zation divisi on factor.
altera corporation 3?3 august 2005 stratix gx device handbook, volume 1 source-synchronous signaling with dpa figure 3?1. stratix gx high-speed interface deserialized in 10 mode notes to figure 3?1 : (1) w = 1, 2, 4, 7, 8, or 10. j = 4, 7, 8, or 10 for non-dpa ( j = 8 or 10 for dpa). w does not have to equal j . when j = 1 or 2, the deserializer is bypassed. when j = 2, the device uses ddrio registers. (2) this figure does not show additional circuitry for clock or data manipulation. figure 3?2. receiver timing diagram stratix gx differential i/ o transmitter operation you can configure any of the stratix g x differential output channels as a transmitter channel. the differential transmitter serializes outbound parallel data. pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 pd9 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 pd9 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 pd9 stratix gx lo g ic array receiver circuit serial shift re g isters parallel re g isters parallel re g isters fast pll (2) rxin+ rxin ? rxclkin+ rxclkin ? w w / j (1) rxloaden txloaden rxloaden internal 1 clock internal 10 clock receiver data input n ? 1 n ? 0 9 8 7 6 5 4 3 2 1 0
3?4 altera corporation stratix gx device handbook, volume 1 august 2005 introduction the logic array sends parallel data to the serdes tr ansmitter circuit when the txloaden signal is asserted. this signal is generated by the high-speed counter circuitry of th e logic array low-frequency clock?s rising edge. the data is then transferre d from the parallel register into the serial shift register by the txloaden signal on the third rising edge of the high-frequency clock. figure 3?3 shows the block diagram of a single serdes transmitter channel and figure 3?4 shows the timing relationship between the data and clocks in stratix gx devices in 10 mode. w is the low-frequency multiplier and j is the data parallelization division factor. figure 3?3. stratix gx high-spee d interface serialized in 10 mode figure 3?4. transmitter timing diagram pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 stratix gx lo g ic array transmitter circuit parallel re g ister serial re g ister fast pll txout+ txout ? w txloaden txloaden internal 1 clock internal 10 clock receiver data input n ? 1 n ? 0 9 8 7 6 5 4 3 2 1 0
altera corporation 3?5 august 2005 stratix gx device handbook, volume 1 source-synchronous signaling with dpa dpa block overview each stratix gx receiver channel featur es a dpa block. the block contains a dynamic phase selector for phase de tection and selection, a serdes, a synchronizer, and a data realigner ci rcuit. you can bypass the dynamic phase aligner without affecting the basic source-synchronous operation of the channel by using a sepa rate deserializer shown in figure 3?5 . the dynamic phase aligner uses both th e source clock and the serial data. the dynamic phase aligner automati cally and continuously tracks fluctuations caused by system variations and self-adjusts to eliminate the phase skew between th e multiplied clock and the serial data. figure 3?5 shows the relationship between stratix gx source-synchronous circuitry and the stratix gx source-synchronous circuitry with dpa. figure 3?5. source-synchronous dpa circuitry note to figure 3?5 : (1) both deserializers are identical. the de serializer operation is described in the ?principles of serdes operation? section. pll dynamic phase ali g ner deserializer stratix gx lo g ic array receiver circuit w 1 rx_in+ rx_in- rx_inclock_p rx_inclock_n 8 deserializer (1) (1)
3?6 altera corporation stratix gx device handbook, volume 1 august 2005 introduction unlike the de-skew function in apex tm 20ke and apex 20kc devices, you do not have to use a fixed trai ning pattern with dpa in stratix gx devices. table 3?1 shows the differences between source-synchronous circuitry with dpa and source-syn chronous circuitry without dpa circuitry in stratix gx devices. dpa input support stratix gx device i/o banks 1 and 2 contain dedicated circuitry to support differential i/o standards at speeds up to 1 gbps with dpa (or up to 840 mbps without dpa). stra tix gx device source-synchronous circuitry supports lvds, lvpecl, and 3.3-v pcml i/o standards, each with a supply voltage of 3.3 v. refer to the high-speed source-synchronous differential i/o interfaces in stratix gx devices chapter of the stratix gx device handbook, volume 2 for more information on these i/o standards. transmitter pins can be either input or output pins for single-ended i/o standards. refer to table 3?2 . interface & fast pll this section describes the number of channels that support dpa and their relationship with the pll in stratix gx devices. ep1sgx10 and ep1sgx25 devices have two dedicated fast plls and ep1sgx40 devices table 3?1. source-synchronous circuitry with & without dpa feature source-synchronous circuitry without dpa with dpa data rate 300 to 840 megabits per second (mbps) 300 mbps to 1 gbps deserialization factors 1, 2, 4, 8, 10 8, 10 clock frequency 10 to 717 mhz 74 to 717 mhz interface pins i/o banks 1 and 2 i/o banks 1 and 2 receiver pins dedicated inputs dedicated inputs table 3?2. bank 1 & 2 input pins input pin type i/o standard rec eiver pin transmitter pin differential differential input only output only single ended single ended input only input or output
altera corporation 3?7 august 2005 stratix gx device handbook, volume 1 source-synchronous signaling with dpa have four dedicated fast plls for clock multiplication. table 3?3 shows the maximum number of channels in each stratix gx device that support dpa. the receiver and transmitter channels are interleaved so that each i/o row in i/o banks 1 and 2 of the device has one receiver channel and one transmitter channel per row. figures 3?6 and 3?7 show the fast pll and channels with dpa layout in ep1sgx10, ep1sgx25, and ep1sgx40 devices. in ep1sgx10 devices, only fast pll 2 supports dpa operations. table 3?3. stratix gx source-synchronous differential i/o resources device fast plls pin count receiver channels (1) transmitter channels (1) receiver & transmitter channel speed (gbps) (2) les ep1sgx10c 2 (3) 672 22 22 1 10,570 ep1sgx10d 2 (3) 672 22 22 1 10,570 ep1sgx25c 2 672 39 39 1 25,660 ep1sgx25d 2 672 39 39 1 25,660 1,020 39 39 1 25,660 ep1sgx25f 2 1,020 39 39 1 25,660 ep1sgx40d 4 (4) 1,020 45 45 1 41,250 ep1sgx40g 4 (4) 1,020 45 45 1 41,250 notes to ta b l e 3 ? 3 : (1) this is the number of receiver or transmitter channels in the source-synchronous (i/o bank 1 and 2) interface of the device. (2) receiver channels operate at 1,000 mbps with dpa. without dpa, the receiver channels operate at 840 mbps. (3) one of the two fast plls in ep1s gx10c and ep1sgx10d devices supports dpa. (4) two of the four fast plls in ep1s gx40d and ep1sgx40g devices support dpa
3?8 altera corporation stratix gx device handbook, volume 1 august 2005 introduction figure 3?6. pll & channel layout in ep1sgx10 & ep1sgx25 devices notes (1) , (2) notes to figure 3?6 : (1) fast pll 1 in ep1sgx10 devices does not support dpa. (2) not all eight phases are used by the re ceiver channel or tr ansmitter channel in non-dpa mode. fast pll 1 (1) fast pll 2 1 receiver 1 receiver 1 transmitter 1 transmitter 1 receiver 1 receiver 1 transmitter 1 transmitter inclk0 inclk1 11 rows for ep1sgx10 devices & 20 rows for ep1sgx25 devices 11 rows for ep1sgx10 devices & 19 rows for ep1sgx25 devices 8 eight-phase clock 8
altera corporation 3?9 august 2005 stratix gx device handbook, volume 1 source-synchronous signaling with dpa figure 3?7. pll & channel layout in ep1sgx40 devices notes (1) , (2) , (3) notes to figure 3?7 : (1) corner plls do not support dpa. (2) not all eight phases are used by the re ceiver channel or tr ansmitter channel in non-dpa mode. (3) the center plls can only clock 20 transceivers in either direction. using fast pll2, you can clock a total of 40 transceivers, 20 in each direction. fast pll 1 fast pll 2 1 receiver 1 receiver 1 transmitter 1 transmitter 1 receiver 1 receiver 1 transmitter 1 transmitter inclk0 pll (1) clkin pll (1) clkin inclk1 23 rows 22 rows 8 eight-phase clock eight-phase clock 8
3?10 altera corporation stratix gx device handbook, volume 1 august 2005 introduction dpa operation the dpa receiver circuitry contains the dynamic phase selector, the deserializer, the synchronizer, and the data realigner (see figure 3?8 ). this section describes the dpa oper ation, synchronization and data realignment. in the serdes with dpa mode, the source clock is fed to the fast pll through the dedicated clock input pins. this clock is multiplied by the multiplication value w to match the serial data rate. for information on the deserializer, see ?principles of serdes operation? on page 3?1 . figure 3?8. dpa receiver circuit note to figure 3?8 : (1) these are phase-matched and retimed high-speed clocks and data. the dynamic phase selector matches the phase of the high-speed clock and data before sending them to the deserializer. the fast pll supplies eight phases of the same clock (each a separate tap from a four-stage differential vco) to all the differential channels associated with the selected fast pll. the dpa circuitry inside each channel locks to a phase closest to the serial data?s phase and sends the retimed data and the selected clock to the deserializer. the dpa circuitry automatically performs this operation and is not something you select. each channel?s dpa circuit can independently choose a different clock phase. the data phase detection and the clock phase selection process is automatic and continuous. the eight phases of the clock give the dpa circuit a granularity of one eighth of the unit interval (ui) or 125 ps at 1gbps. figure 3?9 illustrates the clocks generated by the fast pll circuitry and their relationship to a data stream. rxin+ rxin- inclk+ inclk - fast pll dynamic phase selector deserializer parallel clock synchronizer data reali g ner w clock (1) 1 clock serial data (1) stratix gx lo g ic array dpa receiver circuit gclk rclk reset 8 10 10 dpll_reset
altera corporation 3?11 august 2005 stratix gx device handbook, volume 1 source-synchronous signaling with dpa figure 3?9. fast pll clocks & data input protocols, training pattern & dpa lock time the dynamic phase aligner uses a fast pll for clock multiplication, and the dynamic phase selector for the phase detection and alignment. the dynamic phase aligner uses the high -speed clock out of the dynamic phase selector to deserialize high-speed data and the receiver's source synchronous operations. at each rising edge of the clock, the dynamic phase selector determines the phase difference between the cl ock and the data and automatically compensates for the phase difference between the data and clock. clock a data input clock b clock c clock d clock c' clock d' clock a' clock b' d0 d1 d2 d3 d4 d5 d n
3?12 altera corporation stratix gx device handbook, volume 1 august 2005 introduction the actual lock time for different data patterns varies depending on the data?s transition density (how often the data switches between 1 and 0) and jitter characteristic. the dpa circ uitry is designed to lock onto any data pattern with sufficient transition density, so the circuitry works with current and future protocols. experime nts and simulations show that the dpa circuitry locks when the data patterns listed in table 3?4 are repeated for the specified number of times. there are other suitable patterns not shown in table 3?4 and/or pattern lengths, but the lock time may vary. the circuit can adjust for any phase variation that may occur during operation. phase synchronizer each receiver has its own phase synchronizer. the receiver phase synchronizer aligns the ph ase of the parallel data from all the receivers to one global clock. the synchronizers in each channel consist of a 4-bit deep and j -bit wide fifo buffer. the parallel clock writes to the fifo buffer and the global clock ( gclk ) reads from the fifo buffer. the global and parallel clock inputs into the sy nchronizers must have identical frequencies and differ only in phase. the fifo buffer never becomes full or empty (because the source and receive signals are frequency locked) when operating within the dpa spec ifications, and the operation does not require an empty/full flag or read/write enable signals. receiver data realignment in dpa mode while dpa operation aligns the inco ming clock phase to the incoming data phase, it does not guarantee th e parallelization boundary or byte boundary. when the dynamic phase aligne r realigns the data bits, the bits may be shifted out of byte alignment, as shown in figure 3?10 . table 3?4. training patterns for different protocols protocols training pattern number of repetitions spi-4, npsi ten 0?s, ten 1?s ( 00000000001111111111 ) 256 rapidio four 0?s, four 1?s ( 00001111 ) or one 1, two 0?s, one 1, four 0?s ( 10010000 ) other designs eight alternating 1?s and 0?s ( 10101010 or 01010101 ) sfi-4, xsbi not specified
altera corporation 3?13 august 2005 stratix gx device handbook, volume 1 source-synchronous signaling with dpa figure 3?10. misaligned captured bits the dynamic phase selector and sync hronizer align the clock and data based on the power-up of both commu nicating devices, and the channel to channel skew. however, the dynamic phase selector and synchronizer cannot determine the byte boundary, and the data may need to be byte-aligned. the dynamic phase alig ner?s data realignment circuitry shifts data bits to co rrect bit misalignments. the stratix gx circuitry contains a da ta-realignment feature controlled by the logic array. stratix gx devices perform data realignment on the parallel data after the deserializatio n block. the data realignment can be performed per channel for more flexibility. the data alignment operation requires a state machine to recogniz e a specific pattern. the procedure requires the bits to be slipped on th e data stream to correctly align the incoming data to the start of the byte boundary. the dpa uses its realignment circui try and the global clock for data realignment. either a device pin or the logic array asserts the internal rx_channel_data_align node to activate the dpa data-realignment circuitry. switching this node from low to high activates the realignment circuitry and the data being transfer red to the logic array is shifted by one bit. the data realignment block ca nnot be bypassed. however, if the rx_channel_data_align is not turned on (through the altvlds megawizard plug-in manager), or when it is not toggled, it only acts as a register latency. a state machine and additional logic can monitor the incoming parallel data and compare it against a known pattern. if the incoming data pattern does not match the known pattern, you can activate the rx_channel_data_align node again. repeat this process until the realigner detects the desired match between the known data pattern and incoming parallel data pattern. 0 1 2 3 4 5 6 7 3 4 5 6 7 0 1 2 correct alignment incorrect alignment
3?14 altera corporation stratix gx device handbook, volume 1 august 2005 introduction the dpa data-realignment circuitry allows further realignment beyond what the j multiplication factor allows. you can set the j multiplication factor to be 8 or 10. however, becaus e data must be co ntinuously clocked in on each low-speed clock cycle, th e upcoming bit to be realigned and previous n ? 1 bits of data are selected each time the data realignment logic?s counter passes n ? 1. at this point the data is selected entirely from bit-slip register 3 (see figure 3?11 ) as the counter is reset to 0. the logic array receives a new valid byte of data on the next divided low speed clock cycle. figure 3?11 shows the data real ignment logic output selection from data in the data realignment register 2 and data realignment register 3 based on its current counter value upon continuous request of data slipping from the logic array. figure 3?11. dpa data realigner use the rx_channel_data_align signal within the device to activate the data realigner. you can use internal logic or an external pin to control the rx_channel_data_align signal. to ensure the rising edge of the rx_channel_data_align signal is latched into the control logic, the rx_channel_data_align signal should stay hi gh for at least two low- frequency clock cycles. d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 one bit slipped zero bits slipped. counter = 0 d10 is the upcoming bit to be slipped. bit slip register 2 bit slip register 3 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 seven more bits slipped one bit slipped. counter = 1 d21 is the upcoming bit to be slipped. bit slip register 2 bit slip register 3 d99 d98 d97 d96 d95 d94 d93 d92 d91 d90 d89 d18 d87 d86 d85 d84 d83 d82 d81 d80 one more bit slipped one more bit slipped eight bits slipped. counter = 8 d98 is the upcoming bit to be slipped. bit slip register 2 bit slip register 3 d119 d118 d117 d116 d115 d114 d113 d112 d111 d110 nine bits slipped. counter = 9 d119 is the upcoming bit to be slipped. bit slip register 2 bit slip register 3 d119 d118 d117 d116 d115 d114 d113 d112 d111 d110 d109 d108 d107 d106 d125 d124 d123 d102 d101 d100 10 bits slipped. counter = 0 real data will resume on the next byte. bit slip register 2 bit slip register 3 d99 d98 d97 d96 d95 d94 d93 d92 d91 d90
altera corporation 3?15 august 2005 stratix gx device handbook, volume 1 source-synchronous signaling with dpa to manage the alignment procedure, a state machine should be built in the fpga logic array to generate th e realignment signal. the following guidelines outline the requirements for this state machine. the design must include an input synchronizing register to ensure that data is synchronized to the w / j clock. after the state machine, use another synchronizing register to capture the generated rx_channel_data_align signal and synchronize it to the w / j clock. because the skew in the path from the output of this synchronizing register to the pll is undefined, the state machine must generate a pulse that is high for two w / j clock periods. to guarantee the state machine does not incorrectly generate multiple rx_channel_data_align pulses to shift a single bit, the state machine must hold the rx_channel_data_align signal low for at least three 1 clock periods between pulses.
3?16 altera corporation stratix gx device handbook, volume 1 august 2005 introduction
altera corporation 4?1 february 2005 4. stratix gx architecture logic array blocks each lab consists of 10 les, le carry chains, lab control signals, local interconnect, lut chain, and register chain connection lines. the local interconnect transfers signals between les in the same lab. lut chain connections transfer the output of one le?s lut to the adjacent le for fast sequential lut connections within the same lab. register chain connections transfer the ou tput of one le?s register to the adjacent le?s register within an lab. the quartus ? ii compiler places associated logic within an lab or adjacent labs, allowing the use of local, lut chain, and register chain connections for performance and area efficiency. figure 4?1 shows the stratix ? gx lab. figure 4?1. stratix gx lab structure lab interconnects the lab local interconnect can drive les within the same lab. the lab local interconnect is driven by column and row interconnects and le outputs within the same lab. ne ighboring labs, m512 ram blocks, direct link interconnect from adjacent block direct link interconnect to adjacent block row interconnects of variable speed & length column interconnects of variable speed & length three-sided architecture?local interconnect is driven from either side by columns & labs, & from above by rows local interconnect lab direct link interconnect from adjacent block direct link interconnect to adjacent block sgx51004-1.0
4?2 altera corporation stratix gx device handbook, volume 1 february 2005 logic array blocks m4k ram blocks, or dsp blocks from th e left and right can also drive an lab?s local interconnect through the direct link connection. the direct link connection feature minimi zes the use of row and column interconnects, providing higher performance and flexibility. each le can drive 30 other les through fast local and direct link interconnects. figure 4?2 shows the direct link connection. figure 4?2. direct link connection lab control signals each lab contains dedicated logic for driving control signals to its les. the control signals include two clocks, two clock enables, two asynchronous clears, synchronous cl ear, asynchronous preset/load, synchronous load, and add/subtract control signals. this gives a maximum of 10 control signals at a ti me. although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. each lab can use two clocks and two clock enable signals. each lab?s clock and clock enable signals are linked. for exampl e, any le in a particular lab using the labclk1 signal also uses labclkena1 . if the lab uses both the rising and falling ed ges of a clock, it also uses both lab-wide clock signals. de-asserting the clock enable signal turns off the lab-wide clock. lab direct link interconnect to ri g ht direct link interconnect from ri g ht lab, trimatrix memory block, dsp block, or ioe output direct link interconnect from left lab, trimatrix memory block, dsp block, or ioe output local interconnect direct link interconnect to left
altera corporation 4?3 february 2005 stratix gx device handbook, volume 1 stratix gx architecture each lab can use two asynchronous clear signals and an asynchronous load/preset signal. the as ynchronous load acts as a preset when the asynchronous load data input is tied high. with the lab-wide addnsub control signal, a single le can implement a one-bit adder and subtractor. this saves le resources and improves performance for logic functions such as dsp correlators and signed multipliers that alternate between addition and subtraction depending on data. the lab row clocks [7..0] and lab local interconnect generate the lab- wide control signals. the multitrack tm interconnect?s inherent low skew allows clock and control signal di stribution in addition to data. figure 4?3 shows the lab control signal generation circuit. figure 4?3. lab-wide control signals logic elements the smallest unit of logic in the stra tix gx architecture, the le, is compact and provides advanced feat ures with efficient logic utilization. each le contains a four-input lut, which is a function generator that can implement any function of four variable s. in addition, each le contains a programmable register and carry chain with carry select capability. a single le also supports dynamic single bit addition or subtraction mode selectable by an lab-wide control signal. each le drives all types of interconnects: local, row, column, lut chain, register chain, and direct link interconnects. see figure 4?4 . labclkena1 labclk2 labclk1 labclkena2 asyncload or labpre syncload dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect labclr1 labclr2 synclr addnsub 8
4?4 altera corporation stratix gx device handbook, volume 1 february 2005 logic elements figure 4?4. stratix gx le each le?s programmable register can be configured for d, t, jk, or sr operation. each register has data, true asynchronous load data, clock, clock enable, clear, and asynchronous load/preset inputs. global signals, general-purpose i/o pins, or any internal logic can drive the register?s clock and clear control signals. ei ther general-purpose i/o pins or internal logic can drive the clock enable, preset, asynchronous load, and asynchronous data. the asynchronous load data input comes from the data3 input of the le. for combinator ial functions, the register is bypassed and the output of the lut dr ives directly to the outputs of the le. each le has three outputs that drive the local, row, and column routing resources. the lut or register ou tput can drive these three outputs independently. two le outputs drive column or row and direct link routing connections and one drives local interconnect resources. this allows the lut to drive one output while the register drives another output. this feature, called register packing, improves device utilization because the device can use the register and the lut for unrelated functions. another special packing mo de allows the register output to feed back into the lut of the same le so that the register is packed with labclk1 labclk2 labclr2 labpre/aload carry-in1 carry-in0 lab carry-in clock & clock enable select lab carry-out carry-out1 carry-out0 look-up ta b l e (lut) carry chain row, column, and direct link routin g row, column, and direct link routin g programmable register prn/ald clrn d q ena register bypass packed register select chip-wide reset labclkena1 labclkena2 synchronous load and clear lo g ic lab-wide synchronous load lab-wide synchronous clear asynchronous clear/preset/ load lo g ic data1 data2 data3 data4 lut chain routin g to next le labclr1 local routin g re g ister chain output a data addnsub register feedback re g ister chain routin g from previous le
altera corporation 4?5 february 2005 stratix gx device handbook, volume 1 stratix gx architecture its own fan-out lut. this provides another mechanism for improved fitting. the le can also drive out registered and unregistered versions of the lut output. lut chain & register chain in addition to the three general routing outputs, the les within an lab have lut chain and register chain ou tputs. lut chain connections allow luts within the same lab to cascad e together for wide input functions. register chain outputs allow register s within the same lab to cascade together. the register chain output allows an lab to use luts for a single combinatorial function and the register s to be used for an unrelated shift register implementation. these resources speed up connections between labs while saving local in terconnect resources. see ?multitrack interconnect? on page 4?11 for more information on lut chain and register chain connections. addnsub signal the le?s dynamic adder/subtractor feature saves logic resources by using one set of les to implement both an adder and a subtractor. this feature is controlled by the lab-wide control signal addnsub . the addnsub signal sets the lab to perform either a + b or a ? b. the lut computes addition, and subtraction is computed by adding the two?s complement of the intended subtractor . the lab-wide signal converts to two?s complement by inverting the b bits within the lab and setting carry-in = 1 to add one to the least si gnificant bit (lsb). the lsb of an adder/subtractor must be placed in the first le of the lab, where the lab-wide addnsub signal automatic ally sets the carry-in to 1. the quartus ii compiler automatically plac es and uses the adder/subtractor feature when using adder/subtra ctor parameterized functions. le operating modes the stratix gx le can operate in one of the following modes: normal mode dynamic arithmetic mode each mode uses le resources differently. in each mode, eight available inputs to the le?the four data inputs from the lab local interconnect; carry-in0 and carry-in1 from the previous le; the lab carry-in from the previous carry-chain lab; and the register chain connection? are directed to different destinatio ns to implement the desired logic function. lab-wide signals provid e clock, asynchronous clear, asynchronous preset lo ad, synchronous clear, synchronous load, and
4?6 altera corporation stratix gx device handbook, volume 1 february 2005 logic elements clock enable control for the register. these lab-wide signals are available in all le modes. the addnsub control signal is allowed in arithmetic mode. the quartus ii software, in conjunct ion with parameterized functions such as library of parameterized mo dules (lpm) function s, automatically chooses the appropriate mode for co mmon functions such as counters, adders, subtractors, and arithmetic functions. if required, you can also create special-purpose functions that specify which le operating mode to use for optimal performance. normal mode the normal mode is suitable for general logic applications and combinatorial functions. in normal mo de, four data inputs from the lab local interconnect are inputs to a four-input lut (see figure 4?5 ). the quartus ii compiler automaticall y selects the carry-in or the data3 signal as one of the inputs to th e lut. each le can use lut chain connections to drive its combinatorial ou tput directly to the next le in the lab. asynchronous load data fo r the register comes from the data3 input of the le. les in normal mode support packed registers. figure 4?5. le in normal mode note to figure 4?5 : (1) this signal is only allowed in normal mode if the le is at the end of an adder/subtractor chain. data1 4-input lut data2 data3 cin (from cout of previous le) data4 addnsub (lab wide) clock (lab wide) ena (lab wide) aclr (lab wide) aload (lab wide) ald/pre clrn d q ena a data sclear (lab wide) sload (lab wide) re g ister chain connection lut chain connection re g ister chain output row, column, and direct link routin g row, column, and direct link routin g local routin g register feedback (1)
altera corporation 4?7 february 2005 stratix gx device handbook, volume 1 stratix gx architecture dynamic arithmetic mode the dynamic arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. an le in dynamic arithmetic mode uses four 2-input luts configurable as a dynamic adder/subtractor. the first two 2-input luts compute two summations based on a possible carry-in of 1 or 0; the other two luts generate carry outputs for the two chains of the ca rry select circuitry. as shown in figure 4?6 , the lab carry-in signal selects either the carry-in0 or carry-in1 chain. the selected chain?s logic level in turn determines which parallel sum is generated as a combinatorial or registered output. for example, when implementing an adder, the sum output is the selection of two possible calculated sums: data1 + data2 + carry-in0 or data1 + data2 + carry-in1 . the other two luts use the data1 and data2 signals to generate two possible carry-out signals?one for a carry of 1 and the other for a carry of 0. the carry-in0 signal acts as the carry select for the carry-out0 output and carry-in1 acts as the carry select for the carry-out1 output. les in arithmetic mode can drive out registered and unregistered versions of the lut output. the dynamic arithmetic mode also of fers clock enable, counter enable, synchronous up/down control, sync hronous clear, sy nchronous load, and dynamic adder/subtrac tor options. the lab local interconnect data inputs generate the counter enable and synchronous up/down control signals. the synchronous clear and synchronous load options are lab-wide signals that affect all registers in the lab. the quartus ii software automatically places any re gisters that are not used by the counter into other labs. the addnsub lab-wide signal controls whether the le acts as an adder or subtractor.
4?8 altera corporation stratix gx device handbook, volume 1 february 2005 logic elements figure 4?6. le in dynamic arithmetic mode note to figure 4?6 : (1) the addnsub signal is tied to the carry input for the first le of a carry chain only. carry-select chain the carry-select chain provides a very fast carry-select function between les in arithmetic mode. the carry-sel ect chain uses th e redundant carry calculation to increase the speed of ca rry functions. the le is configured to calculate outputs for a possible carry-in of 1 and carry-in of 0 in parallel. the carry-in0 and carry-in1 signals from a lower-order bit feed forward into the higher-order bit via the parallel carry chain and feed into both the lut and the next portion of the carry chain. carry- select chains can begin in any le within an lab. the speed advantage of the carry-select chain is in the parallel pre-computation of carry chains. because the lab carry-in selects the precomputed carry ch ain, not every le is in th e critical path. only the propagation delay between lab carry-in generation (le 5 and le 10) are now part of the critical path. th is feature allows the stratix gx architecture to implement high-spe ed counters, adde rs, multipliers, parity functions, and compar ators of arbitrary width. figure 4?7 shows the carry-select circuitry in an lab for a 10-bit full adder. one portion of the lut generates the sum of two bits using the input signals and the appr opriate carry-in bit; the sum is routed to the output of the le. the register can be bypassed for simple adders or used data1 lut data2 data3 addnsub (lab wide) clock (lab wide) ena (lab wide) aclr (lab wide) ald/pre clrn d q ena a data re g ister chain connection lut lut lut carry-out1 carry-out0 lab carry-in carry-in0 carry-in1 (1) sclear (lab wide) sload (lab wide) lut chain connection re g ister chain output row, column, and direct link routin g row, column, and direct link routin g local routin g aload (lab wide) register feedback
altera corporation 4?9 february 2005 stratix gx device handbook, volume 1 stratix gx architecture for accumulator functions. another portion of the lut generates carry- out bits. an lab-wide carry in bit selects which chain to use for the addition of given inputs. the ca rry-in signal for each chain, carry-in0 or carry-in1 , selects the carry-out to carry forward to the carry-in signal of the next-higher-order bit. th e final carry-out signal is routed to an le, where it is fed to local, row, or column interconnects. the quartus ii compiler automatically creates carry chain logic during design processing, or you can create it manually during design entry. parameterized functions such as lpm functions autom atically take advantage of carry chains for the appropriate functions. the quartus ii compiler creates carr y chains longer than 10 les by linking labs together automatically. for enhanced fitting, a long carry chain runs vertically a llowing fast horizontal connections to trimatrix ? memory and dsp blocks. a carry chai n can continue as far as a full column.
4?10 altera corporation stratix gx device handbook, volume 1 february 2005 logic elements figure 4?7. carry select chain clear & preset logic control lab-wide signals control the logic for the register?s clear and preset signals. the le directly supports an asynchronous clear and preset function. the register preset is achi eved through the asynchronous load of a logic high. the direct asynch ronous preset does not require a not-gate push-back technique. strati x gx devices support simultaneous preset/ asynchronous load, and clea r signals. an asynchronous clear signal takes precedence if both signals are asserted simultaneously. each lab supports up to two clears and one preset signal. in addition to the clear and preset ports, stratix gx devices provide a chip-wide reset pin ( dev_clrn ) that resets all registers in the device. an option set before compilation in the qu artus ii software controls this pin. this chip-wide reset overrides all other control signals. le4 le3 le2 le1 a1 b1 a2 b2 a3 b3 a4 b4 sum1 sum2 sum3 sum4 le10 le9 le8 le7 a7 b7 a8 b8 a9 b9 a10 b10 sum7 le6 a6 b6 sum6 le5 a5 b5 sum5 sum8 sum9 sum10 01 01 lab carry-in lab carry-out lut lut lut lut data1 lab carry-in data2 carry-in0 carry-in1 carry-out0 carry-out1 sum
altera corporation 4?11 february 2005 stratix gx device handbook, volume 1 stratix gx architecture multitrack interconnect in the stratix gx architecture, co nnections between les, trimatrix memory, dsp blocks, and device i/o pins are provided by the multitrack interconnect structure with directdrive tm technology. the multitrack interconnect consists of continuous, performance-optimized routing lines of different lengths an d speeds used for inter- and intra- design block connectivity. the quartu s ii compiler autom atically places critical design paths on faster interconnects to improve design performance. directdrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement within the device. the multitrack interconnect and directdrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycl es that typically follow design changes and additions. the multitrack interconnect consists of row and column interconnects that span fixed distances. a routing structure with fixed length resources for all devices allows predictable and repeatable performance when migrating through different device densities. dedicated row interconnects route signals to and from labs, dsp blocks, and trimatrix memory within the same row. these row resources include: direct link interconnects between labs and adjacent blocks. r4 interconnects traversing four blocks to the right or left. r8 interconnects traversing eigh t blocks to the right or left. r24 row interconnects for high-speed access across the length of the device. the direct link interconnect allows an lab, dsp block, or trimatrix memory block to drive into the local in terconnect of its left and right neighbors and then back into itself . only one side of a m-ram block interfaces with direct link and row interconnects. this provides fast communication between adjacent labs and/or blocks without using row interconnect resources. the r4 interconnects span four labs, three labs and one m512 ram block, two labs and one m4k ram block, or two labs and one dsp block to the right or left of a source lab. these resources are used for fast row connections in a four-lab region . every lab has its own set of r4 interconnects to drive either left or right. figure 4?8 shows r4 interconnect connections from an lab. r4 interconnects can drive and be driven by dsp blocks and ram blocks and horizontal ioes. for lab interfacing, a primary lab or lab neighbor can drive a given r4 interconnect. for r4 interconnects th at drive to the right, the primary lab and right neighbor can drive on to the interconnect. for r4 interconnects that drive to the left, the primary lab and its left neighbor
4?12 altera corporation stratix gx device handbook, volume 1 february 2005 multitrack interconnect can drive on to the interconnect. r4 interconnects can drive other r4 interconnects to extend the range of labs they can drive. r4 interconnects can also drive c4 an d c16 interconnects for connections from one row to another. additional ly, r4 interconnects can drive r24 interconnects. figure 4?8. r4 interconnect connections notes to figure 4?8 : (1) c4 interconnects can drive r4 interconnects. (2) this pattern is repeated for every lab in the lab row. the r8 interconnects span eight la bs, m512 or m4k ram blocks, or dsp blocks to the right or left from a sour ce lab. these resources are used for fast row connections in an eight-lab region. every lab has its own set of r8 interconnects to drive either left or right. r8 interconnect connections between labs in a row are similar to the r4 connections shown in figure 4?8 , with the exception that they connect to eight labs to the right or left, not four. like r4 interconnects, r8 interconnects can drive and be driven by all types of architecture blocks. r8 interconnects can drive other r8 interconnects to ex tend their range as well as c8 interconnects for row-to-row connections. one r8 interconnect is faster than two r4 interconnects connected together. r24 row interconnects span 24 labs and provide the fastest resource for long row connections between labs, trimatrix memory, dsp blocks, and ioes. the r24 row interconnects can cross m-ram blocks. r24 row interconnects drive to other row or column interconnects at every fourth primary lab (2) r4 interconnect driving left adjacent lab can drive onto another lab's r4 interconnect c4, c8, and c16 column interconnects (1) r4 interconnect driving right lab neighbor lab neighbor
altera corporation 4?13 february 2005 stratix gx device handbook, volume 1 stratix gx architecture lab and do not drive directly to lab local interconnects. r24 row interconnects drive lab local interconnects via r4 and c4 interconnects. r24 interconnects can drive r24, r4, c16, and c4 interconnects. the column interconnect operates si milarly to the row interconnect and vertically routes signals to and from labs, trimatrix memory, dsp blocks, and ioes. each column of labs is served by a dedicated column interconnect, which vertically routes signals to and from labs, trimatrix memory and dsp blocks, and horizontal ioes. these column resources include: lut chain interconne cts within an lab register chain intercon nects within an lab c4 interconnects traversing a distance of four blocks in up and down direction c8 interconnects traversing a dist ance of eight blocks in up and down direction c16 column interconnects for high -speed vertical routing through the device stratix gx devices include an enhanc ed interconnect structure within labs for routing le output to le input connections faster using lut chain connections and register chain connections. the lut chain connection allows the comb inatorial output of an le to directly drive the fast input of the le right below it, bypassing the local interconnect. these resources can be used as a high-s peed connection for wide fan-in functions from le 1 to le 10 in th e same lab. the register chain connection allows the regi ster output of one le to connect directly to the register input of the next le in the lab for fast shift registers. the quartus ii compiler automatically takes advantage of these resources to improve utilization and performance. figure 4?9 shows the lut chain and register chain interconnects.
4?14 altera corporation stratix gx device handbook, volume 1 february 2005 multitrack interconnect figure 4?9. lut chain & register chain interconnects the c4 interconnects span four labs , m512, or m4k blocks up or down from a source lab. every lab has its own set of c4 interconnects to drive either up or down. figure 4?10 shows the c4 interc onnect connections from an lab in a column. the c4 interconnects can drive and be driven by all types of architecture bloc ks, including dsp blocks, trimatrix memory blocks, and vertical ioes. for lab interconnection, a primary lab or its lab neighbor can drive a given c4 interconnect. c4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. le 1 le 2 le 3 le 4 le 5 le 6 le 7 le 8 le 9 le 10 lut chain routing to adjacent le local interconnect register chain routing to adjacen t le's register input local interconnect routing among les in the lab
altera corporation 4?15 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?10. c4 interc onnect connections note (1) note to figure 4?10 : (1) each c4 interconnect can drive either up or down four rows. c8 interconnects span eight labs, m512, or m4k blocks up or down from a source lab. every lab has its own set of c8 interconnects to drive either up or down. c8 interconnect connections between the labs in a column are similar to the c4 connections shown in figure 4?10 with the exception that they connect to eigh t labs above and below. the c8 c4 interconnect drives local and r 4 interconnects up to four rows adjacent lab can drive onto nei g hborin g lab's c4 interconnect c4 interconnect driving up c4 interconnect driving down lab row interconnect local interconnect
4?16 altera corporation stratix gx device handbook, volume 1 february 2005 multitrack interconnect interconnects can drive and be driven by all types of architecture blocks similar to c4 interconnects. c8 interconnects can drive each other to extend their range as well as r8 interconnects for column-to-column connections. c8 interconnects are fa ster than two c4 interconnects. c16 column interconnects span a length of 16 labs and provide the fastest resource for long column connections between labs, trimatrix memory blocks, dsp blocks, and ioes. c16 interconnects can cross m- ram blocks and also drive to row and column interconnects at every fourth lab. c16 interconnects drive lab local interconnects via c4 and r4 interconnects and do not drive lab local interconnects directly. all embedded blocks communicate with the logic array similar to lab- to-lab interfaces. each block (that is, trimatrix memory and dsp blocks) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. these blocks also have direct link interconnects for fast co nnections to and from a neighboring lab. all blocks are fed by the row lab clocks, labclk[7..0] .
altera corporation 4?17 february 2005 stratix gx device handbook, volume 1 stratix gx architecture table 4?1 shows the stratix gx device?s routing scheme. table 4?1. stratix gx device routing scheme source destination lut chain register chain local interconnect direct link interconnect r4 interconnect r8 interconnect r24 interconnect c4 interconnect c8 interconnect c16 interconnect le m512 ram block m4k ram block m-ram block dsp blocks column ioe row ioe lut chain v register chain v local interconnect vvvvvvv direct link interconnect v r4 interconnect vvvvv r8 interconnect vvv r24 interconnect vvvv c4 interconnect vv v c8 interconnect vvv c16 interconnect vvvv le vvvvvv vv m512 ram block vvvv vv m4k ram block vvvv vv m-ram block vv dsp blocks vvvv vv column ioe vvvv row ioe v vvvvv
4?18 altera corporation stratix gx device handbook, volume 1 february 2005 trimatrix memory trimatrix memory trimatrix memory consists of three types of ram blocks: m512, m4k, and m-ram blocks. although these me mory blocks are different, they can all implement various types of memory with or without parity, including true dual-port, simple du al-port, and single-port ram, rom, and fifo buffers. table 4?2 shows the size and features of the different ram blocks. table 4?2. trimatrix memory features (part 1 of 2) memory feature m512 ram block (32 18 bits) m4k ram block (12836bits) m-ram block (4k 144 bits) maximum performance (1) (1) (1) true dual-port memory vv simple dual-port memory vvv single-port memory vvv shift register vv rom vv (2) fifo buffer vvv byte enable vv parity bits vvv mixed clock mode vvv memory initialization vv simple dual-port memory mixed width support vvv true dual-port memory mixed width support vv power-up conditions outputs cl eared outputs cleared outputs unknown register clears input and output registers input and output registers output registers mixed-port read- during-write unknown output/old data unknown output/old data unknown output
altera corporation 4?19 february 2005 stratix gx device handbook, volume 1 stratix gx architecture memory modes trimatrix memory blocks include inpu t registers that synchronize writes and output registers to pipeline designs and improve system performance. m4k and m-ram memory blocks offer a true dual-port mode to support any combination of two-port operations: two reads, two writes, or one read and one write at two different clock frequencies. figure 4?11 shows true dual-port memory. figure 4?11. true dual-port memory configuration in addition to true dual-port memory , the memory blocks support simple dual-port and single-por t ram. simple dual-port memory supports a simultaneous read and write and can ei ther read old data before the write configurations 512 1 256 2 128 4 64 8 64 9 32 16 32 18 4k 1 2k 2 1k 4 512 8 512 9 256 16 256 18 128 32 128 36 64k 8 64k 9 32k 16 32k 18 16k 32 16k 36 8k 64 8k 72 4k 128 4k 144 notes to ta b l e 4 ? 2 : (1) see the dc & switching characteristics chapter of the stratix gx device handbook, volume 1 for maximum performance information. (2) the m-ram block does not support memory initializations. however, the m-ram block can emulate a rom function using a dual-port ram bock. the stratix gx device must write to the dual- port memory once and then disable the write-enable ports afterwards. table 4?2. trimatrix memory features (part 2 of 2) memory feature m512 ram block (32 18 bits) m4k ram block (12836bits) m-ram block (4k 144 bits) data a [ ] address a [ ] wren a clock a clocken a q a [ ] aclr a data b [ ] address b [ ] wren b clock b clocken b q b [ ] aclr b ab
4?20 altera corporation stratix gx device handbook, volume 1 february 2005 trimatrix memory occurs or just read th e don?t care bits. sing le-port memory supports non-simultaneous reads and writes, but the q[] port outputs the data once it has been written to the memo ry (if the outputs are not registered) or after the next rising edge of the cl ock (if the outputs are registered). for more information, see the trimatrix embedded memory blocks in stratix & stratix gx devices chapter of the stratix gx device handbook, volume 2 . figure 4?12 shows these different ram memory port configurations for trimatrix memory. figure 4?12. simple dual-port & singl e-port memory configurations note to figure 4?12 : (1) two single-port memory blocks can be implemented in a single m4k block as long as each of the two independent block sizes is equal to or less than half of the m4k block size. the memory blocks also enable mixed-width data ports for reading and writing to the ram ports in dual-por t ram configuration. for example, the memory block can be wr itten in 1 mode at port a and read out in 16 mode from port b. trimatrix memory architecture can implement pipelined ram by registering both the input and outp ut signals to the ram block. all trimatrix memory block inputs are registered providing synchronous write cycles. in synchronous operatio n, the memory block generates its own self-timed strobe write enable ( wren ) signal derived from the global data[ ] wraddress[ ] wren inclock inclocken inaclr rdaddress[ ] rden q[ ] outclock outclocken outaclr data[ ] address[ ] wren inclock inclocken inaclr q[ ] outclock outclocken outaclr single-port memory (1) simple dual-port memory
altera corporation 4?21 february 2005 stratix gx device handbook, volume 1 stratix gx architecture or regional clock. in contrast, a circuit using asynchronous ram must generate the ram wren signal while ensuring its data and address signals meet setup and hold time specifications relative to the wren signal. the output registers can be bypassed. flow-through reading is possible in the simple dual-port mo de of m512 and m4k ram blocks by clocking the read enable and read ad dress registers on the negative clock edge and bypassing the output registers. two single-port memory blocks can be implemented in a single m4k block as long as each of the two indepe ndent block sizes is equal to or less than half of the m4k block size. the quartus ii software automatically implements larger memory by combining multiple trimatrix memory blocks. for example, two 256 16-bit ram blocks can be co mbined to form a 256 32-bit ram block. memory performance does n ot degrade for memory blocks using the maximum number of words availa ble in one memory block. logical memory blocks using less than the maximum number of words use physical blocks in parallel, eliminating any external control logic that would increase delays. to create a la rger high-speed memory block, the quartus ii software automatically co mbines memory blocks with le control logic. parity bit support the memory blocks support a parity bit for each byte. the parity bit, along with internal le logic, can implement parity checking for error detection to ensure data integrity. you can also use parity-size data words to store user-specified control bits . in the m4k and m-ram blocks, byte enables are also available for data in put masking during write operations. shift register support you can configure embedded memory blocks to implement shift registers for dsp applications such as pseudo-random number generators, multi- channel filtering, auto-correlation, and cross-correlation functions. these and other dsp applications require local data storage, traditionally implemented with standard flip-flops, which can quickly consume many logic cells and routing resources for la rge shift registers. a more efficient alternative is to use embedded memory as a shift register block, which saves logic cell and routing resources and provides a more efficient implementation with th e dedicated circuitry. the size of a w m n shift register is determined by the input data width ( w ), the length of the taps ( m ), and the number of taps ( n ). the size of a w m n shift register must be less than or equal to the maximum number of memory bits in the resp ective block: 576 bits for the m512
4?22 altera corporation stratix gx device handbook, volume 1 february 2005 trimatrix memory ram block and 4,608 bits for the m4 k ram block. the total number of shift register outputs (number of taps n width w ) must be less than the maximum data width of the ram bl ock (18 for m512 blocks, 36 for m4k blocks). to create larger shift regist ers, the memory blocks are cascaded together. data is written into each address locati on at the falling edge of the clock and read from the address at the rising edge of the clock. the shift register mode logic automatically controls the positive and negative edge clocking to shift the data in one clock cycle. figure 4?13 shows the trimatrix memory block in the shift register mode. figure 4?13. shift register memory configuration memory block size trimatrix memory provides three different memory sizes for efficient application support. the large number of m512 blocks are ideal for designs with many shallow first-in fi rst-out (fifo) buffers. m4k blocks provide additional resources for ch annelized functions that do not require large amounts of storage. the m-ram blocks provide a large m -bit shift re g ister w w m -bit shift re g ister m -bit shift re g ister m -bit shift re g ister w w w w w w w m n shift re g ister n numbe r of taps
altera corporation 4?23 february 2005 stratix gx device handbook, volume 1 stratix gx architecture single block of ram ideal for data packet storage. the different-sized blocks allow stratix gx devices to ef ficiently support variable-sized memory in designs. the quartus ii software automatical ly partitions the user-defined memory into the embedded memory bloc ks using the most efficient size combinations. you can also manually assign the memory to a specific block size or a mixture of block sizes. m512 ram block the m512 ram block is a simple dual-port memory block and is useful for implementing small fifo buffers, dsp, and clock domain transfer applications. each block contains 576 ram bits (including parity bits). m512 ram blocks can be configured in the following modes: simple dual-port ram single-port ram fifo rom shift register when configured as ram or rom, you can use an initialization file to pre-load the memory contents. the memory address depths and outp ut widths can be configured as 512 1, 256 2, 128 4, 64 8 (64 9 bits with parity), and 32 16 (32 18 bits with parity). mixed-widt h configurations are also possible, allowing different read and write widths. table 4?3 summarizes the possible m512 ram block configurations. table 4?3. m512 ram block configur ations (simple dual-port ram) read port write port 512 1 256 2 128 4 64 8 32 16 64 9 32 18 512 1 v v vvv 256 2 v v vvv 128 4 vvv v 64 8 vv v 32 16 vvv v 64 9 v 32 18 v
4?24 altera corporation stratix gx device handbook, volume 1 february 2005 trimatrix memory when the m512 ram block is configured as a shift register block, a shift register of size up to 576 bits is possible. the m512 ram block can also be configured to support serializer and deserializer applications. by using the mixed-width support in combination with ddr i/o standards, the block can function as a serdes to support low-speed serial i/o standards using global or regional clocks. see ?i/o structure? on page 4?96 for details on dedicated serdes in stratix gx devices. m512 ram blocks can have different cl ocks on its inputs and outputs. the wren , datain , and write address registers are all clocked together from one of the two cl ocks feeding the block. the read address, rden , and output registers can be clocked by ei ther of the two cl ocks driving the block. this allows the ram block to operate in read/write or input/output clock modes. only the ou tput register can be bypassed. the eight labclk signals or local interconnect can drive the inclock , outclock , wren , rden , inclr , and outclr signals. because of the advanced interconnect between th e lab and m512 ram blocks, les can also control the wren and rden signals and the ram clock, clock enable, and asynchronous clear signals. figure 4?14 shows the m512 ram block control signal generation logic. the ram blocks within stratix gx de vices have local interconnects to allow les and interconnects to dr ive into ram blocks. the m512 ram block local interconnect is driven by the r4, r8, c4, c8, and direct link interconnects from adjacent labs. the m512 ram blocks can communicate with labs on either the left or righ t side through these row interconnects or with lab columns on the left or right side with the column interconnects. up to 10 direct link input connections to the m512 ram block are possible from the left adjacent labs and another 10 possible from the right adjacent lab. m512 ram outputs can also connect to left and right labs throug h 10 direct link interconnects. the m512 ram block has equal opportunity for access and performance to and from labs on either its left or right side. figure 4?15 shows the m512 ram block to logic array interface.
altera corporation 4?25 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?14. m512 ram block control signals inclocken outclock inclock outclocken rden wren dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect inclr outclr 8 local interconnect local interconnect
4?26 altera corporation stratix gx device handbook, volume 1 february 2005 trimatrix memory figure 4?15. m512 ram block lab row interface m4k ram blocks the m4k ram block includes support for true dual-port ram. the m4k ram block implements buffers for a wide variety of applications such as storing processor code, implem enting lookup schemes, and implementing larger memory applications. each block contains 4,608 ram bits (including parity bits). m4k ram blocks can be configured in the following modes: true dual-port ram simple dual-port ram single-port ram fifo rom shift register when configured as ram or rom, you can use an initialization file to pre-load the memory contents. dataout m512 ram block datain clocks 10 direct link interconnect from adjacent lab direct link interconnect to adjacent lab direct link interconnect from adjacent lab direct link interconnect to adjacent lab small ram block local interconnect region c4 and c8 interconnects r4 and r8 interconnects control si g nals address lab row clocks 2 8
altera corporation 4?27 february 2005 stratix gx device handbook, volume 1 stratix gx architecture the memory address depths and outp ut widths can be configured as 4,096 1, 2,048 2, 1,024 4, 512 8 (or 512 9 bits), 256 16 (or 256 18 bits), and 128 32 (or 128 36 bits). the 128 32- or 36-bit configuration is not available in the true dual-port mode. mixed-width configurations are also possible, allowing different read and write widths. tables 4?4 and 4?5 summarize the possible m4k ram block configurations. when the m4k ram block is configured as a shift register block, you can create a shift register up to 4,608 bits ( w m n ). table 4?4. m4k ram block confi gurations (simple dual-port) read port write port 4k 1 2k 2 1k 4 512 8 256 16 128 32 512 9 256 18 128 36 4k 1 vvvv v v 2k 2 vvvv v v 1k 4 vvvv v v 512 8 vvvv v v 256 16 vvvv v v 128 32 vvvv v v 512 9 vv v 256 18 vv v 128 36 vv v table 4?5. m4k ram block confi gurations (true dual-port) port a port b 4k 1 2k 2 1k 4 512 8 256 16 512 9 256 18 4k 1 vvvvv 2k 2 vvvvv 1k 4 vvvvv 512 8 vvvvv 256 16 vvvvv 512 9 vv 256 18 vv
4?28 altera corporation stratix gx device handbook, volume 1 february 2005 trimatrix memory m4k ram blocks support byte writes when the write port has a data width of 16, 18, 32, or 36 bits. the byte enables al low the input data to be masked so the device can write to specific bytes. the unwritten bytes retain the previous written value. table 4?6 summarizes the byte selection. the m4k ram blocks allow for differ ent clocks on their inputs and outputs. either of the two clocks feeding the block can clock m4k ram block registers ( renwe , address, byte enable, datain , and output registers). only the output register can be bypassed. the eight labclk signals or local interconnects can drive the control signals for the a and b ports of the m4k ram block. les can also control the clock_a , clock_b , renwe_a , renwe_b , clr_a , clr_b , clocken_a , and clocken_b signals, as shown in figure 4?16 . the r4, r8, c4, c8, and direct link interconnects from adjacent labs drive the m4k ram block local inte rconnect. the m4k ram blocks can communicate with labs on either the left or righ t side through these row resources or with lab columns on either the right or left with the column resources. up to 10 direct link inpu t connections to the m4k ram block are possible from the left adjacent labs and another 10 possible from the right adjacent lab. m4k ram block outputs can also connect to left and right labs through 10 direct link interconnects each. figure 4?17 shows the m4k ram block to logic array interface. table 4?6. byte enable for m4k blocks notes (1) , (2) byteena[3..0] datain 18 datain 36 [0] = 1 [8..0] [8..0] [1] = 1 [17..9] [17..9] [2] = 1 ? [26..18] [3] = 1 ? [35..27] notes to ta b l e 4 ? 6 : (1) any combination of byte enables is possible. (2) byte enables can be used in the same manner with 8-bit words, that is, in 16 and 32 modes.
altera corporation 4?29 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?16. m4k ram bl ock control signals figure 4?17. m4k ram block lab row interface clocken_a renwe_a clock_a alcr_a alcr_b renwe_b dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect clocken_b clock_b 8 local interconnect local interconnect local interconnect local interconnect local interconnect dataout m4k ram block datain address 10 direct link interconnect from adjacent lab direct link interconnect to adjacent lab direct link interconnect from adjacent lab direct link interconnect to adjacent lab m4k ram block local interconnect region c4 and c8 interconnects r4 and r8 interconnects lab row clocks clocks byte enable control si g nals 8
4?30 altera corporation stratix gx device handbook, volume 1 february 2005 trimatrix memory m-ram block the largest trimatrix memory block, the m-ram block, is useful for applications where a large volume of data must be stored on-chip. each block contains 589,824 ram bits (inc luding parity bits). the m-ram block can be configured in the following modes: true dual-port ram simple dual-port ram single-port ram fifo ram you cannot use an initialization file to initialize the contents of a m-ram block. all m-ram block contents powe r up to an undefined value. only synchronous operation is supported in the m-ram block, so all inputs are registered. output registers ca n be bypassed. the memory address and output width can be configured as 64k 8 (or 64k 9bits), 32k 16 (or 32k 18 bits), 16k 32 (or 16k 36 bits), 8k 64 (or 8k 72 bits), and 4k 128 (or 4k 144 bits). the 4k 128 configuration is unavailable in true dual-port mode because there are a total of 144 data output drivers in the block. mixed-widt h configurations are al so possible, allowing different read and write widths. tables 4?7 and 4?8 summarize the possible m-ram block configurations: table 4?7. m-ram block configur ations (simple dual-port) read port write port 64k 9 32k 18 16k 36 8k 72 4k 144 64k 9 vvvv 32k 18 vvvv 16k 36 vvvv 8k 72 vvvv 4k 144 v
altera corporation 4?31 february 2005 stratix gx device handbook, volume 1 stratix gx architecture the read and write operation of the memory is controlled by the wren signal, which sets the ports into either read or write modes. there is no separate read enable ( re ) signal. writing into ram is controlled by both the wren and byte enable ( byteena ) signals for each port. the default value for the byteena signal is high, in which case writing is controlled only by the wren signal. the byte enables are available for th e 18, 36, and 72 modes. in the 144 simple dual-port mode, the two sets of byteena signals ( byteena_a and byteena_b ) are combined to form the necessary 16 byte enables. tables 4?9 and 4?10 summarize the byte selection. table 4?8. m-ram block confi gurations (true dual-port) port a port b 64k 9 32k 18 16k 36 8k 72 64k 9 vvvv 32k 18 vvvv 16k 36 vvvv 8k 72 vvvv table 4?9. byte enable for m-ram blocks notes (1) , (2) byteena[3..0] datain 18 datain 36 datain 72 [0] = 1 [8..0] [8..0] [8..0] [1] = 1 [17..9] [17..9] [17..9] [2] = 1 ? [26..18] [26..18] [3] = 1 ? [35..27] [35..27] [4] = 1 ? ? [44..36] [5] = 1 ? ? [53..45] [6] = 1 ? ? [62..54] [7] = 1 ? ? [71..63]
4?32 altera corporation stratix gx device handbook, volume 1 february 2005 trimatrix memory similar to all ram blocks, m-ram bloc ks can have different clocks on their inputs and output s. all input registers? renwe , datain , address, and byte enable registers?are clocke d together from either of the two clocks feeding the block. the output register can be bypassed. the eight labclk signals or local interconnect can drive the control signals for the a and b ports of the m-ram block. les can also control the clock_a , clock_b , renwe_a , renwe_b , clr_a , clr_b , clocken_a , and clocken_b signals as shown in figure 4?18 . table 4?10. m-ram combined byte selection for 144 mode notes (1) , (2) byteena[15..0] datain 144 [0] = 1 [8..0] [1] = 1 [17..9] [2] = 1 [26..18] [3] = 1 [35..27] [4] = 1 [44..36] [5] = 1 [53..45] [6] = 1 [62..54] [7] = 1 [71..63] [8] = 1 [80..72] [9] = 1 [89..81] [10] = 1 [98..90] [11] = 1 [107..99] [12] = 1 [116..108] [13] = 1 [125..117] [14] = 1 [134..126] [15] = 1 [143..135] notes to ta b l e s 4 ? 9 and 4?10 : (1) any combination of byte enables is possible. (2) byte enables can be used in the same manner with 8-bit words, that is, in 16, 32, 64, and 128 modes.
altera corporation 4?33 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?18. m-ram block control signals one of the m-ram block?s horizontal sides drive the address and control signal (clock, renwe , byteena , etc.) inputs. typically, the horizontal side closest to the device perimeter contains the interfaces. the one exception is when two m-ram blocks are paired ne xt to each other. in this case, the side of the m-ram block opposite the common side of the two blocks contains the input interface. the top and bottom sides of any m-ram block contain data input and output in terfaces to the logic array. the top side has 72 data inputs and 72 data ou tputs for port b, and the bottom side has another 72 data inputs and 72 data outputs for port a. figure 4?19 shows an example floorplan for the ep 1sgx40 device and the location of the m-ram interfaces. clocken_a clock_b clock_a clocken_b aclr_a aclr_b dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect renwe_a renwe_b 8 local interconnect local interconnect local interconnect local interconnect
4?34 altera corporation stratix gx device handbook, volume 1 february 2005 trimatrix memory figure 4?19. ep1sgx40 device with m-ram interface locations note (1) note to figure 4?19 : (1) device shown is an ep1sgx40 device. the number an d position of m-ram blocks varies in other devices. the m-ram block local interconnect is driven by the r4, r8, c4, c8, and direct link interconnects from ad jacent labs. for independent m-ram blocks, up to 10 direct link address and control signal input connections to the m-ram block are possible from the left adjacent labs for m-ram dsp blocks dsp blocks m512 blocks labs m-ram block m-ram block m-ram block m-ram interface to top, bottom, and side opposite of block-to-block border. independent m-ram blocks interface to top, bottom, and side facing device perimeter for easy access to horizontal i/o pins. m-ram block
altera corporation 4?35 february 2005 stratix gx device handbook, volume 1 stratix gx architecture blocks facing to the left, and another 10 possible from the right adjacent labs for m-ram blocks facing to the right. for column interfacing, every m-ram column unit connects to the ri ght and left column lines, allowing each m-ram column unit to communicat e directly with three columns of labs. figures 4?20 through 4?22 show the interface between the m-ram block and the logic array.
4?36 altera corporation stratix gx device handbook, volume 1 february 2005 trimatrix memory figure 4?20. left-facing m-ram to interconnect interface notes (1) , (2) notes to figure 4?20 : (1) only r24 and c16 interconnects cross the m-ram block boundaries. (2) the right-facing m-ram block has interf ace blocks on the right side, but none on the left. b1 to b6 and a1 to a6 orientation is clipped across the vertical axis for right-facing m-ram blocks. m-ram block port b port a row unit interface allows lab rows to drive address and control signals to m-ram block column interface block allows lab columns to drive datain and dataout to and from m-ram block labs in row m-ram boundary labs in column m-ram boundary m512 ram block columns column interface block drives to and from c4 and c8 interconnects lab interface blocks r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b6
altera corporation 4?37 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?21. m-ram row unit interface to interconnect lab row interface block m-ram block 10 up to 24 addressa addressb renwe_a renwe_b byteena a [ ] byteena b [ ] clocken_a clocken_b clock_a clock_b aclr_a aclr_b m-ram block to lab row interface block interconnect region r4 and r8 interconnects c4 and c8 interconnects direct link interconnects
4?38 altera corporation stratix gx device handbook, volume 1 february 2005 trimatrix memory figure 4?22. m-ram column unit interface to interconnect 12 12 column interface block m-ram block to lab row interface block interconnec t region datain dataout lab lab lab c4 and c8 interconnects m-ram block
altera corporation 4?39 february 2005 stratix gx device handbook, volume 1 stratix gx architecture table 4?11 shows the input and output data signal connections for the column units (b1 to b6 and a1 to a6). it also shows the address and control signal input connections to the row units (r1 to r11). table 4?11. m-ram row & column interface unit signals unit interface block input signals output signals r1 addressa[7..0] r2 addressa[15..8] r3 byte_enable_a[7..0] renwe_a r4 - r5 - r6 clock_a clocken_a clock_b clocken_b r7 - r8 - r9 byte_enable_b[7..0] renwe_b r10 addressb[15..8] r11 addressb[7..0] b1 datain_b[71..60] dataout_b[71..60] b2 datain_b[59..48] dataout_b[59..48] b3 datain_b[47..36] dataout_b[47..36] b4 datain_b[35..24] dataout_b[35..24] b5 datain_b[23..12] dataout_b[23..12] b6 datain_b[11..0] dataout_b[11..0] a1 datain_a[71..60] dataout_a[71..60] a2 datain_a[59..48] dataout_a[59..48] a3 datain_a[47..36] dataout_a[47..36] a4 datain_a[35..24] dataout_a[35..24] a5 datain_a[23..12] dataout_a[23..12] a6 datain_a[11..0] dataout_a[11..0]
4?40 altera corporation stratix gx device handbook, volume 1 february 2005 trimatrix memory independent clock mode the memory blocks implement indepe ndent clock mode for true dual- port memory. in this mode, a separate clock is available for each port (ports a and b). clock a controls all registers on the port a side, while clock b controls all registers on the port b side. each port, a and b, also supports independent clock enables and asynchronous clear signals for port a and b registers. figure 4?23 shows a trimatrix memory block in independent clock mode.
altera corporation 4?41 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?23. independent clock mode note (1) note to figure 4?23 : (1) all registers shown have asynchronous clear ports. 8 d ena q d ena q d ena q data a [ ] address a [ ] memory block 256 16 (2) 512 8 1,024 4 2,048 2 4,096 1 data in address a write/read enable data out data in address b write/read enable data out clken a clock a d ena q wren a 8 lab row clocks q a [ ] 8 data b [ ] address b [ ] clken b clock b wren b q b [ ] ena ab ena d q d ena q byteena a [ ] byte enable a byte enable b byteena b [ ] ena d q ena d q ena d q d q write pulse generator write pulse generator
4?42 altera corporation stratix gx device handbook, volume 1 february 2005 trimatrix memory input/output clock mode input/output clock mode can be im plemented for both the true and simple dual-port memory modes. on ea ch of the two ports, a or b, one clock controls all registers for inputs into the memory block: data input, wren , and address. the other clock co ntrols the block?s data output registers. each memory block port, a or b, also supports independent clock enables and asynchronous cl ear signals for input and output registers. figures 4?24 and 4?25 show the memory block in input/output clock mode.
altera corporation 4?43 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?24. input/output clock m ode in true dual-port mode note (1) note to figure 4?24 : (1) all registers shown have asynchronous clear ports. 8 d ena q d ena q d ena q data a [ ] address a [ ] memory block 256 16 (2) 512 8 1,024 4 2,04 8 2 4,096 1 data in address a write/read enable data out data in address b write/read enable data out clken a clock a d ena q wren a 8 lab row clocks q a [ ] 8 data b [ ] address b [ ] clken b clock b wren b q b [ ] ena ab ena d q ena d q ena d q d q d ena q byteena a [ ] byte enable a byte enable b byteena b [ ] ena d q write pulse generator write pulse generator
4?44 altera corporation stratix gx device handbook, volume 1 february 2005 trimatrix memory figure 4?25. input/output clock mode in simple dual-port mode note (1) note to figure 4?25 : (1) all registers shown except the rden register have asynchronous clear ports. read/write clock mode the memory blocks implement read/w rite clock mode for simple dual- port memory. you can use up to two cl ocks in this mode. the write clock controls the block?s data inputs, wraddress , and wren . the read clock controls the data output, rdaddress , and rden . the memory blocks support independent clock enables for each clock and asynchronous clear signals for the read- and write-side registers. figure 4?26 shows a memory block in read/write clock mode. 8 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q wraddress[ ] address[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in read address write address write enable read enable data out outclken inclken wrclock rdclock wren rden 8 lab row clocks to multitrac k interconnect d ena q byteena[ ] byte enable write pulse generator
altera corporation 4?45 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?26. read/write clock mode in simple dual-port mode note (1) note to figure 4?26 : (1) all registers shown except the rden register have asynchronous clear ports. single-port mode the memory blocks also support single-port mode, used when simultaneous reads and writes are not required. see figure 4?27 . a single block in a memory block can support up to two single-port mode ram blocks in the m4k ram bloc ks if each ram block is less than or equal to 2k bits in size. 8 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q wraddress[ ] address[ ] memory block 256 16 512 8 1,024 4 2,04 8 2 4,096 1 data in read address write address write enable read enable data out outclken inclken wrclock rdclock wren rden 8 lab row clocks to multitrac k interconnect d ena q byteena[ ] byte enable write pulse generator
4?46 altera corporation stratix gx device handbook, volume 1 february 2005 digital signal processing block figure 4?27. single-port mode digital signal processing block the most commonly used dsp function s are finite impuls e response (fir) filters, complex fir filter s, infinite impulse response (iir) filters, fast fourier transform (fft) functions, direct cosine transform (dct) functions, and correlators. all of th ese blocks have the same fundamental building block: the multiplier. additionally, some applications need specialized operations such as mul tiply-add and multiply-accumulate operations. stratix gx devices provide dsp blocks to meet the arithmetic requirements of these functions. each stratix gx device has two colu mns of dsp blocks to efficiently implement dsp functions faster than le-based implementations. larger stratix gx devices have more dsp blocks per column (see table 4?12 ). each dsp block can be configured to support up to: eight 9 9-bit multipliers four 18 18-bit multipliers one 36 36-bit multiplier as indicated, the stratix gx dsp block can support one 36 36-bit multiplier in a single dsp block. th is is true for any matched sign multiplications (either unsigned by un signed or signed by signed), but 8 d ena q d ena q d ena q d ena q data[ ] address[ ] ram/rom 256 16 512 8 1,024 4 2,04 8 2 4,096 1 data in address write enable data out outclken inclken inclock outclock write pulse generator wren 8 lab row clocks to multitrac k interconnect
altera corporation 4?47 february 2005 stratix gx device handbook, volume 1 stratix gx architecture the capabilities for dynamic and mixed sign multiplications are handled differently. the following list provides the largest functions that can fit into a single dsp block. 36 36-bit unsigned by unsigned multiplication 36 36-bit signed by si gned multiplication 35 36-bit unsigned by signed multiplication 36 35-bit signed by unsigned multiplication 36 35-bit signed by dynamic sign multiplication 35 36-bit dynamic sign by signed multiplication 35 36-bit unsigned by dynamic sign multiplication 36 35-bit dynamic sign by unsigned multiplication 35 35-bit dynamic sign multiplicati on when the sign controls for each operand are different 36 36-bit dynamic sign multiplicati on when the same sign control is used for both operands 1 this list only shows functions that can fit into a single dsp block. multiple dsp blocks can support larger multiplication functions. figure 4?28 shows one of the columns with surrounding lab rows.
4?48 altera corporation stratix gx device handbook, volume 1 february 2005 digital signal processing block figure 4?28. dsp blocks arranged in columns dsp block column 8 lab rows dsp block
altera corporation 4?49 february 2005 stratix gx device handbook, volume 1 stratix gx architecture table 4?12 shows the number of dsp blocks in each stratix gx device. dsp block multipliers can optionally feed an adder/subtractor or accumulator within the block depend ing on the configuration. this makes routing to les easier, saves le routing resources, and increases performance, because al l connections and blocks are within the dsp block. additionally, the dsp bloc k input registers can efficiently implement shift registers for fir filter applications. figure 4?29 shows the top-level diagram of the dsp block configured for 18 18-bit multiplier mode. figure 4?30 shows the 9 9-bit multiplier configuration of the dsp block. table 4?12. dsp blocks in stratix gx devices notes (1) , (2) device dsp blocks total 9 9 multipliers total 18 18 multipliers total 36 36 multipliers ep1sgx10 6 48 24 6 ep1sgx25 10 80 40 10 ep1sgx40 14 112 56 14 notes to ta b l e 4 ? 1 2 : (1) each device has either the number of 9 9-, 18 18-, or 36 36-bit multipliers shown. the total number of multipliers for each device is not the sum of all the multipliers. (2) the number of supported multiply fu nctions shown is base d on signed/signed or unsigned/unsigned implementations.
4?50 altera corporation stratix gx device handbook, volume 1 february 2005 digital signal processing block figure 4?29. dsp block diagram for 18 18-bit configuration adder/ subtractor/ accumulator 2 adder/ subtractor/ accumulator 1 summation optional pipeline register stage multiplier stage output selection multiplexer optional output register stage clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena optional serial shift register inputs from previous dsp block optional stage configurable as accumulator or dynamic adder/subtractor summation stage for adding four multipliers together optional input register stage with parallel input or shift register configuration optional serial shift register outputs to next dsp block in the column to multitrack interconnect
altera corporation 4?51 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?30. dsp block diagram for 9 9-bit configuration clrn dq ena clrn dq ena clrn dq ena adder/ subtractor/ 1a summation summation clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena adder/ subtractor/ 1b clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena adder/ subtractor/ 2a clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena adder/ subtractor/ 2b clrn dq ena clrn dq ena clrn dq ena output selection multiplexer to multitrack interconnect
4?52 altera corporation stratix gx device handbook, volume 1 february 2005 digital signal processing block the dsp block consists of the following elements: multiplier block adder/output block multiplier block the dsp block multiplier block cons ists of the input registers, a multiplier, and pipeline register fo r pipelining multiply-accumulate and multiply-add/subtract functions as shown in figure 4?31 . figure 4?31. multiplier sub-block within stratix gx dsp block note to figure 4?31 : (1) these signals can be unregister ed or registered once to match data path pipelines if required. clrn dq ena data a data b result to adder blocks shiftout b shiftout a shiftin a shiftin b aclr[3..0] clock[3..0] ena[3..0] optional multiply-accumulate and multiply-add pipeline si g n_a (1) si g n_b (1) clrn dq ena clrn dq ena
altera corporation 4?53 february 2005 stratix gx device handbook, volume 1 stratix gx architecture input registers a bank of optional input registers is located at the input of each multiplier and multiplicand inputs to the multi plier. when these registers are configured for parallel data inputs, they are driven by regular routing resources. you can use a clock signal, asynchronous clear signal, and a clock enable signal to independently co ntrol each set of a and b inputs for each multiplier in the ds p block. you select these control signals from a set of four different clock[3..0] , aclr[3..0] , and ena[3..0] signals that drive the entire dsp block. you can also configure the input registers for a shift register application. in this case, the input registers feed the multiplier and drive two dedicated shift output lines: shiftouta and shiftoutb . the shift outputs of one multiplier block direct ly feed the adjacent multiplier block in the same dsp block (or the next dsp block) as shown in figure 4?32 , to form a shift register chain. this chai n can terminate in an y block, that is, you can create any length of shift regi ster chain up to 224 registers. you can use the input shift registers for fir filter applications. one set of shift inputs can provide data for a filter, and the other are coefficients that are optionally loaded in serial or parallel. when implementing 9 9- and 18 18-bit multipliers, you do not need to implement external shift registers in lab les. you implement all the filter circuitry within the dsp block and its routing resources, saving le and general routing resources for general logic. external registers are needed for shift register inputs when using 36 36-bit multipliers.
4?54 altera corporation stratix gx device handbook, volume 1 february 2005 digital signal processing block figure 4?32. multiplier sub-blocks usin g input shift register connections note (1) note to figure 4?32 : (1) either data a or data b input can be set to a pa rallel input for constant co efficient multiplication. clrn dq ena data a data b a[n] b[n] clrn dq ena clrn dq ena clrn dq ena data a data b a[n e 1] b[n e 1] clrn dq ena clrn dq ena clrn dq ena data a data b a[n e 2] b[n e 2] clrn dq ena clrn dq ena
altera corporation 4?55 february 2005 stratix gx device handbook, volume 1 stratix gx architecture table 4?13 shows the summary of input register modes for the dsp block. multiplier the multiplier supports 9 9-, 18 18-, or 36 36-bit multiplication. each dsp block supports eight possible 9 9-bit or smaller multipliers. there are four multiplier blocks availa ble for multipliers larger than 9 9 bits but smaller than 18 18 bits. there is one multi plier block available for multipliers larger than 18 18 bits but smaller than or equal to 36 36 bits. the ability to have several small multipliers is useful in applications such as video processing. large multipliers greater than 18 18 bits are useful for applications such as the mantissa multiplication of a single-precision floating-point number. the multiplier operands can be sign ed or unsigned numbers, where the result is signed if either input is signed as shown in table 4?14 . the sign_a and sign_b signals provide dynamic control of each operand?s representation: a logic 1 indicates the operand is a signed number, a logic 0 indicates the operand is an unsigned number. these sign signals affect all multipliers and adders within a si ngle dsp block and you can register them to match the data path pipeline. the multipliers are full precision (that is, 18 bits for the 18-bit multiply , 36-bits for the 36-bit multiply, and so on), regardless of whether sign_a or sign_b set the operands as signed or unsigned numbers. table 4?13. input register modes register input mode 9 9 18 18 36 36 parallel input vvv shift register input vv table 4?14. multiplier signed representation data a data b result unsigned unsigned unsigned unsigned signed signed signed unsigned signed signed signed signed
4?56 altera corporation stratix gx device handbook, volume 1 february 2005 digital signal processing block pipeline/post multiply register the output of 9 9- or 18 18-bit multipliers can opti onally feed a register to pipeline multiply-accu mulate and multiply-add/ subtract functions. for 36 36-bit multipliers, this register pipelines the multiplier function. adder/output blocks the result of the multiplier sub-blocks are sent to the adder/output block which consist of an adder/subtrac tor/accumulator unit , summation unit, output select multiplexer, and output registers. the results are used to configure the adder/output block as a pure output, accu mulator, a simple two-multiplier adder, four-multiplier adder, or final stage of the 36-bit multiplier. you can configure the adder/output bloc k to use output registers in any mode, and must use output registers for the accumulator. the system cannot use adder/output blocks independently of the multiplier. figure 4?33 shows the adder and output stages.
altera corporation 4?57 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?33. adder/output blocks note (1) notes to figure 4?33 : (1) adder/output block shown in figure 4?33 is in 18 18-bit mode. in 9 9-bi t mode, there are four adder/subtractor blocks and two summation blocks. (2) these signals are either not registered, registered once , or registered twice to match the data path pipeline. adder/ subtractor/ accumulator1 summation result a result b result c result d addnsub1 (2) accum_sload0 (2) addnsub3 (2) si g na (2) si g nb (2) accum_sload1 (2) accumulator feedback accumulator feedback overflow0 adder/ subtractor/ accumulator2 output selectio n multiplexer output register block overflow1
4?58 altera corporation stratix gx device handbook, volume 1 february 2005 digital signal processing block adder/subtractor/accumulator the adder/subtractor/accumulator is the first level of the adder/output block and can be used as an accumul ator or as an adder/subtractor. adder/subtractor each adder/subtractor/accumulator block can perform addition or subtraction using the addnsub independent control signal for each first- level adder in 18 18-bit mode. there are two addnsub[1..0] signals available in a dsp block for any configuration. for 9 9-bit mode, one addnsub[1..0] signal controls the top two one-level adders and another addnsub[1..0] signal controls the bottom two one-level adders. a high addnsub signal indicates addition, and a low signal indicates subtraction. the addnsub control signal can be unregistered or registered once or twice when feed ing the adder blocks to match data path pipelines. the signa and signb signals serve the same function as the multiplier block signa and signb signals. the only difference is that these signals can be registered up to two times. these signals are tied to the same signa and signb signals from the multiplier and must be connected to the same clocks and control signals. accumulator when configured for accumulation, th e adder/output block output feeds back to the accumulator as shown in figure 4?33 . the accum_sload[1..0] signal synchronously loads the multiplier result to the accumulator output. this signal can be unregistered or registered once or twice. additionally, the overflow signal indicates the accumulator has overflowed or underflowed in accumulation mode. this signal is always registered and must be externally latched in les if the design requires a latched overflow signal. summation the output of the adder/subtract or/accumulator block feeds to an optional summation block. this bloc k sums the outputs of the dsp block multipliers. in 9 9-bit mode, there are two summation blocks providing the sums of two sets of four 9 9-bit multipliers. in 18 18-bit mode, there is one summation providing the sum of one set of four 18 18-bit multipliers.
altera corporation 4?59 february 2005 stratix gx device handbook, volume 1 stratix gx architecture output selection multiplexer the outputs from the various elemen ts of the adder/output block are routed through an output selection multiplexer. based on the dsp block operational mode and user settings, the multiplexer selects whether the output from the multiplier, the adder/subtractor/accumulator, or summation block feeds to the output. output registers optional output registers for the dsp block outputs are controlled by four sets of control signals: clock[3..0] , aclr[3..0] , and ena[3..0] . output registers can be used in any mode. modes of operation the adder, subtractor, and accumulate functions of a dsp block have four modes of operation: simple multiplier multiply-accumulator two-multipliers adder four-multipliers adder 1 each dsp block can only support one mode. mixed modes in the same dsp block is not supported. simple multiplier mode in simple multiplier mode, the dsp block drives the multiplier sub-block result directly to the output with or without an output register. up to four 18 18-bit multipliers or eight 9 9-bit multipliers can drive their results directly out of one dsp block. see figure 4?34 .
4?60 altera corporation stratix gx device handbook, volume 1 february 2005 digital signal processing block figure 4?34. simple multiplier mode note to figure 4?34 : (1) these signals are not registered or regist ered once to match the data path pipeline. dsp blocks can also implement one 36 36-bit multiplier in multiplier mode. dsp blocks use four 18 18-bit multipliers combined with dedicated adder and internal shift circuitry to achieve 36-bit multiplication. the input shift regist er feature is not available for the 36 36-bit multiplier. in 36 36-bit mode, the device can use the register that is normally a multiplier-result-out put register as a pipeline stage for the 36 36-bit multiplier. figure 4?35 shows the 36 36-bit multiply mode. clrn dq ena data a data b data out shiftout b shiftout a shiftin a shiftin b aclr clock ena signa (1) signb (1) clrn dq ena clrn dq ena clrn dq ena
altera corporation 4?61 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?35. 36 36 multiply mode notes to figure 4?35 : (1) these signals are not registered or registered once to match the pipeline. (2) these signals are not registered, registered once, or registered twice for latency to match the pipeline. clrn dq ena a[17..0] a[17..0] b[17..0] b[17..0] a[35..18] a[35..18] b[35..18] b[35..18] aclr clock ena si g na (1) si g nb (1) clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena data ou t 36 36 multiplier adder si g na (2) si g nb (2)
4?62 altera corporation stratix gx device handbook, volume 1 february 2005 digital signal processing block multiply-accumulator mode in multiply-accumulator mode (see figure 4?36 ), the dsp block drives multiplied results to the adder/subtra ctor/accumulator block configured as an accumulator. you can implement one or two multiply-accumulators up to 18 18 bits in one dsp block. the first and third multiplier sub- blocks are unused in this mode, since only one multiplier can feed one of two accumulators. the multiply-accu mulator output can be up to 52 bits?a maximum of a 36-bit result with 16 bits of accumulation. the accum_sload and overflow signals are only available in this mode. the addnsub signal can set the accumulator for decimation and the overflow signal indicates underflow condition. figure 4?36. multiply -accumulate mode notes to figure 4?36 : (1) these signals are not registered or regist ered once to match the data path pipeline. (2) these signals are not registered, regi stered once, or registered twice for la tency to match the data path pipeline. two-multipliers adder mode the two-multipliers adder mode uses the adder/subtractor/accumulator block to add or subtract the outputs of the multiplier block, which is useful for applications such as fft functions and complex fir filters. a single dsp block can implement tw o sums or differences from two 18 18-bit multipliers each or four sums or differences from two 9 9-bit multipliers each. clrn dq ena clrn dq ena data a data b data out overflow shiftout b shiftout a shiftin a shiftin b aclr clock ena signa (1) signb (1) clrn dq ena clrn dq ena accumulator addnsub (2) signa (2) signb (2) accum_sload (2)
altera corporation 4?63 february 2005 stratix gx device handbook, volume 1 stratix gx architecture you can use the two-multipliers adder mode for complex multiplications, which are written as: (a + jb) (c + jd) = [(a c) ? (b d)] + j [(a d) + (b c)] the two-multipliers adder mode allows a single dsp block to calculate the real part [(a c) ? (b d)] using one subtractor and the imaginary part [(a d) + (b c)] using one adder, for data widths up to 18 bits. two complex multiplications are possible for data widths up to 9 bits using four adder/subtractor/accumulator blocks. figure 4?37 shows an 18-bit two-multipliers adder. figure 4?37. two-multipliers adder m ode implementing complex multiply four-multipliers adder mode in the four-multipliers adder mode, th e dsp block adds the results of two first -stage adder/subtractor blocks. one sum of four 18 18-bit multipliers or two different su ms of two sets of four 9 9-bit multipliers can be implemented in a single dsp block. the product width for each multiplier must be the same size. th e four-multipliers adder mode is useful for fir filter applications. figure 4?38 shows the four multipliers adder mode. subtractor 36 36 18 18 18 37 a 18 (a c) ? (b d) (real part) adder 36 36 18 18 37 a 18 18 18 (a d) + (b c) (ima g inary part) 18 18 18 dsp block c b d d b c
4?64 altera corporation stratix gx device handbook, volume 1 february 2005 digital signal processing block figure 4?38. four-multipliers adder mode notes to figure 4?38 : (1) these signals are not registered or regist ered once to match the data path pipeline. (2) these signals are not registered, regi stered once, or registered twice for la tency to match the data path pipeline. clrn dq ena data a data b shiftin a shiftin b aclr clock ena si g na (1) si g nb (1) clrn dq ena clrn dq ena clrn dq ena data a data b clrn dq ena clrn dq ena adder/subtractor clrn dq ena data a data b clrn dq ena clrn dq ena clrn dq ena data a data b shiftout b shiftout a clrn dq ena clrn dq ena adder/subtractor addnsub1 (2) si g na (2) si g nb (2) clrn dq ena data ou t addnsub3 (2) summation
altera corporation 4?65 february 2005 stratix gx device handbook, volume 1 stratix gx architecture for fir filters, the dsp block combines the four-multipliers adder mode with the shift register inputs. one set of shift inputs contains the filter data, while the other holds the coefficients loaded in serial or parallel. the input shift register eliminates the need for shift registers external to the dsp block (that is, implemented in les). this architecture simplifies filter design since the dsp block implemen ts all of the filter circuitry. one dsp block can implement an entire 18-bit fir filter with up to four taps. for fir filters larger than four taps, dsp blocks can be cascaded with additional adder stages implemented in les. table 4?15 shows the different number of multipliers possible in each dsp block mode according to size. these modes allow the dsp blocks to implement numerous applications for dsp including ffts, complex fir, fir, and 2d fir filters, equalizers, iir, correlators, matrix multiplication and many other functions. dsp block interface stratix gx device dsp block outputs can cascade down within the same dsp block column. dedicated connec tions between dsp blocks provide fast connections between the shift register inputs to cascade the shift register chains. you can cascade dsp blocks for 9 9- or 18 18-bit fir filters larger than four taps, with ad ditional adder stages implemented in les. if the dsp block is configured as 36 36 bits, the adder, subtractor, or accumulator stages are implemented in les. each dsp block can route the shift register chain out of the bloc k to cascade two full columns of dsp blocks. table 4?15. multiplier size & c onfigurations per dsp block dsp block mode 9 9 18 18 36 36 (1) multiplier eight multipliers with eight product outputs four multipliers with four product outputs one multiplier with one product output multiply-accumulator two multiply and accumulate (52 bits) two multiply and accumulate (52 bits) ? two-multipliers adder four sums of two multiplier products each two sums of two multiplier products each ? four-multipliers adder two sums of four multiplier products each one sum of four multiplier products each ? note to table 4?15 : (1) the number of supported multiply functions shown is based on signed/sig ned or unsigned/unsigned implementations.
4?66 altera corporation stratix gx device handbook, volume 1 february 2005 digital signal processing block the dsp block is divided into eight bl ock units that interface with eight lab rows on the left and right. each block unit can be considered half of an 18 18-bit multiplier sub-block with 18 inputs and 18 outputs. a local interconnect region is associated with each dsp block. like an lab, this interconnect region can be fed with 10 direct link interconnects from the lab to the left or right of the dsp block in the same row. all row and column routing resources can access the dsp block?s local interconnect region. the outputs also work sim ilarly to lab outputs as well. nine outputs from the dsp block can drive to the left lab through direct link interconnects and nine can drive to the right lab though direct link interconnects. all 18 outputs can drive to all types of row and column routing. outputs can drive right- or left-column routing. figures 4?39 and 4?40 show the dsp block interfaces to lab rows. figure 4?39. dsp block interconnect interface a1[17..0] b1[17..0] a2[17..0] b2[17..0] a3[17..0] b3[17..0] a4[17..0] b4[17..0] oa[17..0] ob[17..0] oc[17..0] od[17..0] oe[17..0] of[17..0] og[17..0] oh[17..0] dsp block multitrack interconnec t multitrack interconnect
altera corporation 4?67 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?40. dsp block interface to interconnect a bus of 18 control signals feeds the entire dsp block. these signals include clock[0..3] clocks, aclr[0..3] asynchronous clears, ena[1..4] clock enables, signa , signb signed/unsigned control signals, addnsub1 and addnsub3 addition and subtraction control signals, and accum_sload[0..1] accumulator synchronous loads. the lab lab row interface block dsp block row structure 10 [17..0] [17..0] dsp block to lab row interface block interconnect region 1 8 inputs per row 1 8 outputs per row r4 and r 8 interconnects c4 and c 8 interconnects direct link interconnect from adjacent lab nine direct link outputs to adjacent labs direct link interconnect from adjacent lab 18 18 18 control 3 9 9 10
4?68 altera corporation stratix gx device handbook, volume 1 february 2005 plls & clock networks clock signals are routed from lab row clocks and are generated from specific lab rows at the dsp block interface. the lab row source for control signals, data inputs, and outputs is shown in table 4?16 . plls & clock networks stratix gx devices provide a hierarchical clock structure and multiple plls with advanced features. the larg e number of clocking resources in combination with the clock synthesi s precision provid ed by enhanced and fast plls provides a comple te clock management solution. stratix gx devices contain up to four enhanced plls and up to four fast plls. in addition, there are four re ceiver plls and one transmitter pll per transceiver block located on the right side of stratix gx devices. global & hierarchical clocking stratix gx devices provide 16 dedi cated global clock networks, 16 regional clock networks (four per device quadrant), 8 dedicated fast regional clock networks within ep1sgx10 and ep1sgx25, and 16 dedicated fast regional clock ne tworks within ep 1sgx40 devices. table 4?16. dsp block signal sources & destinations lab row at interface control signals generated data inputs data outputs 1 signa a1[17..0] oa[17..0] 2 aclr0 accum_sload0 b1[17..0] ob[17..0] 3 addnsub1 clock0 ena0 a2[17..0] oc[17..0] 4 aclr1 clock1 ena1 b2[17..0] od[17..0] 5 aclr2 clock2 ena2 a3[17..0] oe[17..0] 6 sign_b clock3 ena3 b3[17..0] of[17..0] 7 clear3 accum_sload1 a4[17..0] og[17..0] 8 addnsub3 b4[17..0] oh[17..0]
altera corporation 4?69 february 2005 stratix gx device handbook, volume 1 stratix gx architecture these clocks are organized into a hierar chical clock structure that allows for up to 22 clocks per device region with low skew and delay. this hierarchical clocking scheme provides up to 40 unique clock domains within ep1sgx10 and ep1sgx25 device s, and 48 unique clock domains within ep1sgx40 devices. there are 12 dedicated clock pins ( clk[15..12] , and clk[7..0] ) to drive either the global or regional clock networks. three clock pins drive the top, bottom, and left side of the device. enhanced and fast pll outputs as well as an i/o interfac e can also drive these global and regional clock networks. there are up to 20 recovered clocks ( rxclkout[20..0] ) and up to 5 transmitter clock outputs ( coreclk_out ) which can drive any of the global clock networks ( clk[15..0] ), as shown in figure 4?41 . global clock network these clocks drive throughout the entire device, feeding all device quadrants. the global clock networks can be used as clock sources for all resources within the device ioes, les, dsp blocks, and all memory blocks. these resources can also be used for control signals, such as clock enables and synchronous or asynchrono us clears fed from the external pin. the global clock networks can al so be driven by internal logic for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. figure 4?41 shows the 12 dedicated clk pins and the transceiver cl ocks driving global clock networks.
4?70 altera corporation stratix gx device handbook, volume 1 february 2005 plls & clock networks figure 4?41. global clock resources regional clock network there are four regional clock networks rclk[3..0] within each quadrant of the stratix gx device that are driven by the same dedicated clk[7..0] and clk[15..12] input pins, pll outp uts, or transceiver clocks. the regional clock networks only pert ain to the quadrant they drive into. the regional clock networks provide the lowest clock delay and skew for logic contained wi thin a single quadrant. the clk clock pins symmetrically drive the rclk networks within a particular quadrant, as shown in figure 4?42 . clk[15..12] clk[3..0] clk[7..4] global clock [15..0] transceiver clocks
altera corporation 4?71 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?42. regional clocks fast regional clock network in ep1sgx25 and ep1sgx10 devices, th ere are two fast regional clock networks, fclk[1..0] , within each quadrant, fed by input pins (see figure 4?43 ). in ep1sgx40 devices, there are two fast regional clock networks within each half-quadrant (see figure 4?44 ). the fclk[1..0] clocks can also be used for high fanout control signals, such as asynchronous clears, presets, clock enables, or protocol control signals such as trdy and irdy for pci. dual-purpose fclk pins drive the fast clock networks. all devices have eight fclk pins to drive fast regional clock networks. any i/o pin can drive a clock or control signal onto any fast regional clock network with the addition of a delay. the i/o interconnect drives this signal. rclk[1..0] rclk[3..2] rclk[5..4] rclk[7..6] rclk[15..14] rclk[13..12] rclk[9..8] rclk[11..10 ] clk[15..12] clk[3..0] clk[7..4] regional clocks only drive a device quadrant from specified clk pins, recovered clocks, or plls within that quadrant transceiver clocks
4?72 altera corporation stratix gx device handbook, volume 1 february 2005 plls & clock networks figure 4?43. ep1sgx25 & ep1sgx10 devi ce fast clock pin connections to fast regional clocks fclk[1..0] fclk[1..0] fclk[1..0] fclk[1..0] [3..2] [1..0] [5..4] [7..6] fast clock fast clock fast clock fast clock
altera corporation 4?73 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?44. ep1sgx40 device fast regi onal clock pin connections to fast regional clocks combined resources within each region, there are 22 dist inct dedicated clocking resources consisting of 16 global clock lines, 4 regional clock lines, and 2 fast regional clock lines. multiplexers are used with these clocks to form 8-bit busses to drive lab row clocks, col umn ioe clocks, or row ioe clocks. another multiplexer at the lab level selects two of the eight row clocks to feed the le registers within the lab. see figure 4?45 . [3] fast clock [2] fast clock [1] fast clock [0] [4] [5] [6] [7] fast clock fclk[1..0] fast clock fast clock fast clock fast clock
4?74 altera corporation stratix gx device handbook, volume 1 february 2005 plls & clock networks figure 4?45. regional clock bus ioe clocks have horizontal and vertical block regi ons that are clocked by eight i/o clock signals chosen from the 22-quadrant or half-quadrant clock resources. figures 4?46 and 4?47 show the quadrant and half- quadrant relationship to the i/o cloc k regions, respectively. the vertical regions (column pins) have less cloc k delay than the horizontal regions (row pins). clock [21:0] vertical i/o cell io_clk[7..0] lab row clock [7..0] horizontal i/o cell io_clk[7..0] global clock network [15..0] fast re g ional clock network [1..0] re g ional clock network [3..0] clocks available to a quadrant or half-quadrant
altera corporation 4?75 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?46. ep1sgx25 & ep1sgx 10 device i/o clock groups io_clkf[7:0] io_clke[7:0] io_clka[7:0] io_clkb[7:0] io_clkh[7:0] io_clkg[7:0] 8 8 22 clocks in the quadrant 22 clocks in the quadrant 22 clocks in the quadrant 22 clocks in the quadrant 8 8 8 8 i/o clock region s 13 14 16 15
4?76 altera corporation stratix gx device handbook, volume 1 february 2005 plls & clock networks figure 4?47. ep1sgx40 devi ce i/o clock groups you can use the quartus ii software to control whether a clock input pin is either global, regional, or fast regional. the quartus ii software automatically selects the clocking resources if not specified. enhanced & fast plls stratix gx devices provide robust clock management and synthesis using up to four enhanced plls and four fast plls. these plls increase performance and provide advanced cl ock interfacing and clock frequency synthesis. with features such as clock switchover, spread spectrum io_clkj[7:0] io_clki[7:0] io_clka[7:0] io_clkb[7:0] 8 22 clocks in the half-quadrant 22 clocks in the half-quadrant 22 clocks in the half-quadrant 22 clocks in the half-quadrant 22 clocks in the half-quadrant 22 clocks in the half-quadrant 22 clocks in the half-quadrant 22 clocks in the half-quadrant 8 8 8 i/o clock regions io_clkl[7:0] io_clkk[7:0] io_clkc[7:0] io_clkd[7:0] 888 8 8 8 8 8 io_clkn[7:0] io_clkm[7:0] io_clkp[7:0] io_clko[7:0] 13 14 17 16 15
altera corporation 4?77 february 2005 stratix gx device handbook, volume 1 stratix gx architecture clocking, programmable bandwidth, phase and delay control, and dynamic pll reconfiguration, the st ratix gx device?s enhanced plls provide you with complete control of your clocks and system timing. the fast plls provide general purpose clocking with multiplication and phase shifting as well as high-speed outputs for high-speed differential i/o support. enhanced and fast plls work together with the stratix gx high-speed i/o and advanc ed clock architecture to provide significant improvements in system performance and bandwidth. the quartus ii software enables th e plls and their features without requiring any external devices. table 4?17 shows which plls are available for each stratix gx device and their type. table 4?18 shows the enhanced pll and fast pll features in stratix gx devices. table 4?17. stratix gx device pll availability device fast plls enhanced plls 123 (1) 4 (1) 789 (1) 10 (1) 5 (2) 6 (2) 11 (3) 12 (3) ep1sgx10 vv vv ep1sgx25 vv vv ep1sgx40 vv vv vvvv notes to table 4?17 : (1) plls 3, 4, 9, and 10 are not available in stratix gx devices. however, these plls are listed in table 4?17 because the stratix gx pll numbering scheme is consistent with stratix devices. (2) plls 5 and 6 each have eight single-e nded outputs or four differential outputs. (3) plls 11 and 12 each have one single-ended output. table 4?18. stratix gx enhanced pll & fast pll features (part 1 of 2) notes (1) ? (8) feature enhanced pll fast pll clock multiplication and division m / ( n post-scale counter) (1) m /(post-scale counter) (2) phase shift down to 156.25-ps increments (3) , (4) down to 125-ps increments (3) , (4) delay shift 250-ps increments for 3 ns clock switchover v pll reconfiguration v programmable bandwidth v spread spectrum clocking v programmable duty cycle vv number of internal clock outputs 6 3 (5)
4?78 altera corporation stratix gx device handbook, volume 1 february 2005 plls & clock networks figure 4?48 shows a top-level diagram of the stratix gx device and the pll floorplan. number of external clock outputs f our differential/eight singled-ended or one single-ended (6) (7) number of feedback clock inputs 4 (8) notes to table 4?18 : (1) the maximum count value is 1024, with a 50% duty cycle setting on the counter. the maximum count value for any other duty cycle setting is 512. (2) for fast plls, m and post-scale counters range from 1 to 32. (3) the smallest phase shif t is determined by the vco period divided by 8. (4) for degree increments, stratix gx devices can shift all outp ut frequencies in increments of at least 45. smaller degree increments are possible depending on the frequency and divide parameters. (5) plls 7 and 8 have two output ports per pll. plls 1 and 2 have three output ports per pll. (6) every stratix gx device has two enhanced plls (plls 5 an d 6) with eight single-ended or four differential outputs each. two additional enhanced plls (plls 11 and 12) in ep1sgx40 devices each have one single-ended output. (7) fast plls can drive to any i/o pin as an external clock. for high-speed differential i/o pins, the device uses a data channel to generate txclkout . (8) every stratix gx device has two enhanced plls with one single-ended or differential external feedback input per pll. table 4?18. stratix gx enhanced pll & fast pll features (part 2 of 2) notes (1) ? (8) feature enhanced pll fast pll
altera corporation 4?79 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?48. pll floorplan figure 4?49 shows the global and regional clock connections from the pll outputs and the clk pins. fpll7clk fpll8clk clk[3..0] 7 1 2 8 11 5 12 6 clk[7..4] clk[15..12] plls high-speed transceivers inclk1 inclk2 inclk3 inclk4 inclk5
4?80 altera corporation stratix gx device handbook, volume 1 february 2005 plls & clock networks figure 4?49. global & regional clock connections from side pins & fast pll outputs note (1) note to figure 4?49 : (1) plls 1,2 7, and 8 are fast plls. plls 7 and 8 do not drive global clocks. figure 4?50 shows the global and regional clocking from enhanced pll outputs and top clk pins. 2 clk0 clk1 clk2 clk3 g0 fpll7clk g1 g2 g3 rclk0 rclk1 rclk2 rclk3 global clocks pll 7 l 0 l 1 g 0 pll 1 pll 2 fpll8clk pll 8 regional clocks l 0 l 1 g 0 l 0 l 1 g 0 l 0 l 1 g 0
altera corporation 4?81 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?50. global & regional cloc k connections from top clock pins & enhanced pll outputs note (1) note to figure 4?50 : (1) plls 5, 6, 11, and 12 are enhanced plls. g12 g13 g14 g15 rclk10 rclk11 rclk2 rclk3 g7 g6 g5 g4 rclk13 rclk12 rclk7 rclk6 pll 12 (4) l0 l1 g0 g1 g2 g3 clk7 clk6 clk5 clk4 pll 6 g0 g1 g2 g3 l0 l1 pll 11 (4) l0 l1 g0 g1 g2 g3 clk13 clk12 clk14 clk15 pll 5 g0 g1 g2 g3 l0 l1 e[0..3] pll12_o ut pll6_ou t[3..0] pll11_out pll5_out[3..0] pll5_fb pll6_fb g lo ba l c lo c k s reg ion a l c lo c k s reg ion a l c lo c k s (1) ( 2 ) (1) ( 2 ) ( 2 ) ( 2 ) (1) (1)
4?82 altera corporation stratix gx device handbook, volume 1 february 2005 plls & clock networks enhanced plls stratix gx devices contain up to four enhanced plls with advanced clock management features. figure 4?51 shows a diagram of the enhanced pll. figure 4?51. stratix gx enhanced pll notes to figure 4?51 : (1) external feedback is available in plls 5 and 6. (2) this external output is available from the g 0 counter for plls 11 and 12. (3) these counters and external outp uts are available in plls 5 and 6. /n char g e pump vco / g 0 / g 1 / g 2 /e0 8 4 global clocks /e1 /e2 i/o buffers (3) /e3 t t t t t t t t lock detect to i/o or g eneral routin g clk0 clk1 fbin pfd / g 3 /l1 /l0 from adjacent pll /m spread spectrum i/o buffers (2) (1) loop filter & filter programmable time delay on each pll port post-scale counters clock switch-over circuitry phase frequency detector vco phase selection selectable at each pll output port vco phase selection affecting all outputs t t t t regional clocks 4
altera corporation 4?83 february 2005 stratix gx device handbook, volume 1 stratix gx architecture clock multiplication & division each stratix gx device enhanced pll provides clock synthesis for pll output ports using m /( n post-scale counter) scaling factors. the input clock is divided by a pre-scale divider, n , and is then multiplied by the m feedback factor. the control loop drives the vco to match f in ( m / n ). each output port has a unique post-scale counter that divides down the high-frequency vco. for multiple pll outputs with different frequencies, the vco is set to the least common multiple of the output frequencies that meets its frequency specifications. then, the post-scale dividers scale down the output frequency for each output port. for example, if output frequencies requ ired from one pll are 33 and 66 mhz, set the vco to 330 mhz (the least comm on multiple in the vco?s range). there is one pre-scale divider, n , and one multiply divider, m , per pll, with a range of 1 to 512 on each. th ere are two post-scale dividers ( l ) for regional clock output po rts, four counters ( g ) for global clock output ports, and up to four counters ( e ) for external clock outputs, all ranging from 1 to 512. the quartus ii soft ware automatically chooses the appropriate scaling factors acco rding to the input frequency, multiplication, and division values entered. clock switchover to effectively develop high-reliability network systems, clocking schemes must support multiple clocks to provide redundancy. for this reason, stratix gx device enhanced plls support a flexible clock switchover capability. figure 4?52 shows a block diagram of the switchover circuit.the switchover circuit is co nfigurable, so you can define how to implement it. clock-sense circuitry automatically switches from the primary to secondary clock for pll reference when the primary clock signal is not present.
4?84 altera corporation stratix gx device handbook, volume 1 february 2005 plls & clock networks figure 4?52. clock switchover circuitry note to figure 4?52 : (1) pfd: phase frequency detector. there are two possible ways to use the clock switchover feature. you can use automatic switchover circuitry for switching between inputs of the same frequency. fo r example, in a pplications that require a redundant clock with th e same frequency as the primary clock, the switchover state machine generates a signal that controls the multiplexer select input on the bottom of figure 4?52 . in this case, the secondary clock becomes the reference clock for the pll. you can use the clkswitch input for user- or system-controlled switch conditions. this is possible for same-frequency switchover or to switch between inputs of different frequencies. for example, if inclk0 is 66 mhz and inclk1 is 100 mhz, you must control the switchover because the automatic clock-sense circuitry cannot monitor primary and secondary clock frequencies with a frequency difference of more than 20%. th is feature is us eful when clock sources can originate from multi ple cards on the backplane, n counter clkloss clk0 clk1 clk1_bad clk0_bad clkswitch pfd fbclk clock sense smclksw enhanced pll active clock switch-over state machine t muxout
altera corporation 4?85 february 2005 stratix gx device handbook, volume 1 stratix gx architecture requiring a system-controlled swit chover between frequencies of operation. you can use clkswitch together with the lock signal to trigger the switch from a clock that is running but becomes unstable and cannot be locked onto. during switchover, the pll vco continues to run and either slows down or speeds up, generating frequency drift on the pll outputs. the clock switchover transitions without any gl itches. after the switch, there is a finite resynchronization period to lock onto new clock as the vco ramps up. the exact amount of time it takes for the pll to relock relates to the pll configuration and may be adjusted by using the programmable bandwidth feature of the pll. the preliminary specification for the maximum time to relock is 100 s. f for more information on clock switchover, see an313: implementing clock switchover in stratix & stratix gx devices . pll reconfiguration the pll reconfiguration feature enables system logic to change stratix gx device enhanced pll counters and delay elements without reloading a programmer object file ( .pof ). this provides considerable flexibility for frequency synthesis, allowing real-time pll frequency and output clock delay variat ion. you can sweep the pll output frequencies and clock delay in prototype enviro nments. the pll reconfiguration feature can also dynamically or intelligently control system clock speeds or t co delays in end systems. clock delay elements at each pll outp ut port implement variable delay. figure 4?53 shows a diagram of the overall dynamic pll control feature for the counters and the clock delay elements. the config uration time is less than 20 s for the enhanced pll using a input shift clock rate of 25 mhz. the charge pump, loop filt er components, and phase shifting using vco phase taps cannot be dynamically adjusted.
4?86 altera corporation stratix gx device handbook, volume 1 february 2005 plls & clock networks figure 4?53. dynamically programm able counters & delays in stratix gx device enhanced plls pll reconfiguration data is shifted into serial registers from the logic array or external devices. the pll input shift data uses a reference input shift clock. once the last bit of the se rial chain is clocked in, the register chain is synchronously loaded into the pll configuration bits. the shift circuitry also provides an asynchronous clear for the serial registers. programmable bandwidth you have advanced control of the pll bandwidth using the programmable control of the pll loop characteristics, including loop filter and charge pump. the pll?s band width is a measure of its ability to track the input clock and jitter. a high-bandwidth pll can quickly lock onto a reference clock and react to any changes in the clock. it also allows a wide band of input jitter spectrum to pass to the output. a low-bandwidth pll takes longer to lock, but it attenuates all high-frequency jitter components. the quartus ii software can adjust pll characteristics to achieve the desired bandwidth. the programmable bandwidth is tuned by varying the ch arge pump current, loop filter resistor value, high frequency capacitor value, and m counter value. you can manually adjust these values if desired. bandwidth is programmable from 150 khz to 2 mhz. n t t m g t l t e t pfd vco char g e pump loop filter f ref scandata scanclk scanaclr counters and clock delay settings are programmable all output counters and clock delay settings can be programmed dynamically
altera corporation 4?87 february 2005 stratix gx device handbook, volume 1 stratix gx architecture external clock outputs enhanced plls 5 and 6 each support up to eight single-ended clock outputs (or four differential pairs). see figure 4?54 . figure 4?54. external clock outputs for plls 5 & 6 notes to figure 4?54 : (1) each external clock output pin can be us ed as a general purpose output pin from the logic array. these pins ar e multiplexed with ioe outputs. (2) two single-ended output s are possible per output counter?either two outputs of the same frequency and phase or one shifted 180. any of the four external output coun ters can drive the single-ended or differential clock outputs for plls 5 and 6. this means one counter or frequency can drive all output pins available from pll 5 or pll 6. each e 0 counter extclk0_a extclk0_b extclk1_a extclk1_b extclk2_a extclk2_b extclk3_a extclk3_b e 1 counter e 2 counter e 3 counter from ioe (1) from ioe (1) from ioe (1) from ioe (1) from ioe (1) from ioe (1) from ioe (1) from ioe (1) 4 (2)
4?88 altera corporation stratix gx device handbook, volume 1 february 2005 plls & clock networks pair of output pins (four pins total) has dedicated vcc and gnd pins to reduce the output clock?s overall ji tter by providing im proved isolation from switching i/o pins. for plls 5 and 6, each pi n of a single-ended output pair can either be in phase or 180 out of phase. the clock output pin pairs support the same i/o standards as standard output pins (in the top and bottom banks) as well as lvds, lvpecl, 3.3-v pcml, hypertransport technology, differential hstl, and differential sstl. table 4?19 shows which i/o standards the enhanced pll clock pins support. when in single-ended or differential mode, the two outputs operate off the same power supply. both outputs use the same standards in single-ended mode to maintain performance. you can also use the ex ternal clock output pins as user output pins if external enhanc ed pll clocking is not needed. table 4?19. i/o standards supported for enhanced pll pins (part 1 of 2) i/o standard input output inclk fbin pllenable extclk lv t t l vvvv lv c m o s vvvv 2.5 v vv v 1.8 v vv v 1.5 v vv v 3.3-v pci vv v 3.3-v pci-x vv v lvpecl vv v 3.3-v pcml vv v lv d s vv v hypertransport technology vv v differential hstl vv differential sstl v 3.3-v gtl vv v 3.3-v gtl+ vv v 1.5-v hstl class i vv v 1.5-v hstl class ii vv v sstl-18 class i vv v sstl-18 class ii vv v sstl-2 class i vv v sstl-2 class ii vv v
altera corporation 4?89 february 2005 stratix gx device handbook, volume 1 stratix gx architecture enhanced plls 11 and 12 support one single-ended output each (see figure 4?55 ). these outputs do not have their own vcc and gnd signals. therefore, to minimize jitter, do not place switching i/o pins next to this output pin. figure 4?55. external clock outputs for enhanced plls 11 & 12 note to figure 4?55 : (1) for pll 11, this pin is clk13n ; for pll 12 this pin is clk7n . stratix gx devices can drive any enhanc ed pll driven through the global clock or regional clock network to an y general i/o pin as an external output clock. the jitter on the output clock is not guaranteed for these cases. clock feedback the following four feedback modes in stratix gx device enhanced plls allow multiplication and/or phase and delay shifting: zero delay buffer: the external cl ock output pin is phase-aligned with the cloc k input pin for zero delay. external feedback: the exte rnal feedback input pin, fbin , is phase-aligned with the clock input, clk , pin. aligning these clocks allows you to remove clock delay and skew between devices. this mode is only possible for plls 5 and 6. plls 5 and 6 each support sstl-3 class i vv v sstl-3 class ii vv v agp (1 and 2 ) vv v ctt vv v table 4?19. i/o standards supported for enhanced pll pins (part 2 of 2) i/o standard input output inclk fbin pllenable extclk clk13n, i/o, pll11_out or clk6n, i/o, pll12_out (1 ) from internal lo g ic or ioe g 0 counter
4?90 altera corporation stratix gx device handbook, volume 1 february 2005 plls & clock networks feedback for one of the dedicate d external outputs, either one single-ended or one differential pair. in this mode, one e counter feeds back to the pll fbin input, becoming part of the feedback loop. normal mode: if an internal clock is used in this mode, it is phase-aligned to the input clock pin. the external cl ock output pin has a phase delay relative to the clock input pin if connected in this mode. you define which internal clock output from the pll should be phase-aligned to th e internal clock pin. no compensation: in this mode, the pll does not compensate for any clock networks or external clock outputs. phase & delay shifting stratix gx device enhanced plls provide advanced programmable phase and clock delay shifting. for phase shifting, you can specify a phase shift (in degrees or time units) for each pll clock output port or for all outputs together in one shift. phas e-shifting values in time units are allowed with a resolution range of 160 to 420 ps. this resolution is a function of frequency input and the mu ltiplication and division factors. in other words, it is a function of the vco period equal to one-eighth of the vco period. each cl ock output counter can choose a different phase of the vco period from up to eight taps. you can use this clock output counter along with an initial setting on the post-scale counter to achieve a phase-shift range for the entire period of the output clock. the phase tap feedback to the m counter can shift all outputs to a single phase or delay. the quartus ii software automatically sets the phase taps and counter settings according to the phase shift entered. in addition to the phase-shift feature, the fine tune clock delay shift feature provides advanced time delay shift control on each of the four pll outputs. each pll output shifts in 250-ps incremen ts for a range of ?3.0 ns to +3.0 ns between any two ou tputs using discret e delay elements. total delay shift between any two pll outputs must be less than 3 ns. for example, shifts on outputs of ?1 an d +2 ns is allowed, but not ?1 and +2.5 ns. there is some delay variation due to process, voltage, and temperature. only the clock delay shif t blocks can be controlled during system operation for dynamic clock delay control. spread-spectrum clocking the stratix gx device?s enhanced plls use spread-spectrum technology to reduce electromagnetic interferen ce generation from a system by distributing the energy over a broa der frequency range. the enhanced
altera corporation 4?91 february 2005 stratix gx device handbook, volume 1 stratix gx architecture pll typically provides 0.5 % down spread modulation using a triangular profile. the modulation frequency is programmable. enabling spread spectrum for a pll affects all of its outputs. lock detect the lock output indicates that there is a stable clock output signal in phase with the reference clock. withou t any additional ci rcuitry, the lock signal may toggle as the pll begins tr acking the reference clock. you may need to gate the lock signal for use as a system control. the lock signal from the locked port can drive the logic array or an output pin. whenever the pll loses lock for any reason (be it excessive inclk jitter, clock switchover, pll reconfiguration, power supply noise etc.), the pll must be reset with the areset signal for correct phase shift operation. if the phase relationship between the in put clock versus output clock, and between different output clocks from the pll is not important in the design, then the pll need not be reset. f see the stratix gx fpga errata sheet for more information on implementing the gated lock signal in the design. programmable duty cycle the programmable duty cycle allows enhanced plls to generate clock outputs with a variable duty cycle. this featur e is supported on each enhanced pll post-scale counter ( g 0.. g 3, l 0.. l 3, e 0.. e 3). the duty cycle setting is achieved by a low and high time count setting for the post-scale dividers. the quartus ii software uses the frequency input and the required multiply or divide rate to determine the duty cycle choices. advanced clear & enable control there are several control signals for cl earing and enabling plls and their outputs. you can use these signals to control pll resynchronization and gate pll output clocks for low-power applications. the pllenable pin is a dedicated pin that enables/disables plls. when the pllenable pin is low, the clock ou tput ports are driven by gnd and all the plls go out of lock. when the pllenable pin goes high again, the plls relock and resynchronize to th e input clocks. you can choose which plls are controlled by the pllenable signal by connecting the pllenable input port of the altpll megafunction to the common pllenable input pin.
4?92 altera corporation stratix gx device handbook, volume 1 february 2005 plls & clock networks the areset signals are reset/re synchronization inputs for each pll. the areset signal should be asserted ev ery time the pll loses lock to guarantee correct phase relationship between the pll output clocks. users should include the areset signal in designs if any of the following conditions are true: pll reconfiguration or clock switchover enables in the design. phase relationships between output clocks need to be maintained after a loss of lock condition the device input pins or logic el ements (les) can drive these input signals. when driven high, the pll counters resets, clearing the pll output and placing the pll out of lock . the vco sets back to its nominal setting (~700 mhz). when driven low again, the pll resynchronizes to its input as it relocks. if the target vco frequency is below this nominal frequency, then the output frequency st arts at a higher value than desired as the pll locks. if the syst em cannot tolerate this, the clkena signal can disable the output cloc ks until the pll locks. the pfdena signals control the phase frequency detector (pfd) output with a programmable gate. if you disa ble the pfd, the vco operates at its last set value of control voltage and frequency with some long-term drift to a lower frequency. the system continues running when the pll goes out of lock or the input clock is disabled. by maintaining the last locked frequency, the system has time to store its current settings before shutting down. you can either us e your own control signal or a clkloss status signal to trigger pfdena . the clkena signals control the enhanced pll regional and global outputs. each regional and global output port has its own clkena signal. the clkena signals synchronously disable or enable the clock at the pll output port by gating the outputs of the g and l counters. the clkena signals are registered on the falling edge of the counter output clock to enable or disable the clock without glitches. figure 4?56 shows the waveform example for a pll clock port enable. the pll can remain locked independent of the clkena signals since the loop-related counters are not affected. this feature is useful for applications that require a low power or sleep mode. upon re-enabling, the pll does not need a resynchronization or relock period. the clkena signal can also disable clock outputs if the system is not to lerant to frequency overshoot during resynchronization. the extclkena signals work in the same way as the clkena signals, but they control the external clock output counters ( e 0, e 1, e 2, and e 3). upon re-enabling, the pll does not need a resynchronization or relock period
altera corporation 4?93 february 2005 stratix gx device handbook, volume 1 stratix gx architecture unless the pll is using external feedback mode. in order to lock in external feedback mode, the external output must drive the board trace back to the fbin pin. figure 4?56. extclkena signals fast plls stratix gx devices contain up to four fast plls with high-speed serial interfacing ability, along with general-purpose features. figure 4?57 shows a diagram of the fast pll. counter output clkena clkout
4?94 altera corporation stratix gx device handbook, volume 1 february 2005 plls & clock networks figure 4?57. stratix gx device fast pll notes to figure 4?57 : (1) in high-speed differential i/o support mode, this high-s peed pll clock feeds the serd es. stratix gx devices only support one rate of data transfer per fast p ll in high-speed differential i/o support mode. (2) this signal is a high-speed differential i/o support serdes control signal. clock multiplication & division the stratix gx device?s fast plls provide clock synthesis for pll output ports using m /(post scaler) scaling factors. the input clock is multiplied by the m feedback factor. each output port has a unique post scale counter to divide down the high-frequency vc o. there is one multiply divider, m , per fast pll with a range of 1 to 32. there are two post scale l dividers for regional and/or lvds interface clocks, and g 0 counter for global clock output port; all range from 1 to 32. in the case of a high-speed differenti al interface, you can set the output counter to 1 to allow the high-speed vco frequency to drive the serdes. external clock outputs each fast pll supports differential or single-ended outputs for source-synchronous transmitters or for general-purpose external clocks. there are no dedicated external cloc k output pins. any i/o pin can be driven by the fast pll global or regi onal outputs as an external output char g e pump vco g 0 8 clock input pfd l 1 l 0 m loop filter phase frequency detector vco phase selection selectable at each pll output port post-scale counters global or re g ional clock global or re g ional clock global or re g ional clock diffioclk2 (2) diffioclk1 (2) txload_en rxload_en global or re g ional clock (1)
altera corporation 4?95 february 2005 stratix gx device handbook, volume 1 stratix gx architecture pin. the i/o standards supported by any particular bank determines what standards are possible for an exte rnal clock output driven by the fast pll in that bank. table 4?20 shows the i/o standards supported by fast pll input pins. table 4?20. fast pll port input pin i/o standards i/o standard input inclk pllenable lv t t l vv lv c m o s vv 2.5 v v 1.8 v v 1.5 v v 3.3-v pci 3.3-v pci-x lvpecl v 3.3-v pcml v lv d s v hypertransport technology v differential hstl v differential sstl 3.3-v gtl v 3.3-v gtl+ v 1.5v hstl class i v 1.5v hstl class ii v sstl-18 class i v sstl-18 class ii v sstl-2 class i v sstl-2 class ii v sstl-3 class i v sstl-3 class ii v agp (1 and 2 ) v ctt v
4?96 altera corporation stratix gx device handbook, volume 1 february 2005 i/o structure phase shifting stratix gx device fast plls have ad vanced clock shift capability that enables programmable phase shifts. you can enter a phase shift (in degrees or time units) for each pll clock output port or for all outputs together in one shift. you can perform phase shifting in time units with a resolution range of 150 to 400 ps. this resolution is a function of the vco period. control signals the fast pll has the same lock output, pllenable input, and areset input control signals as the enhanced pll. for more information on high-speed differential i/o support, see the high-speed source-synchronous differential i/o interfaces in stratix gx devices chapter of the stratix gx device handbook, volume 2 . i/o structure ioes provide many features, including: dedicated differential and single-ended i/o buffers 3.3-v, 64-bit, 66-mhz pci compliance 3.3-v, 64-bit, 133-mhz pci-x 1.0 compliance joint test action group (jtag) boundary-scan test (bst) support differential on-chip termination for lvds i/o standard programmable pull-up during configuration output drive strength control slew-rate control tri-state buffers bus-hold circuitry programmable pull-up resistors programmable input and output delays open-drain outputs dq and dqs i/o pins double-data rate (ddr) registers the ioe in stratix gx devices contains a bidirectional i/o buffer, six registers, and a latch for a complete embedded bidirectional single data rate or ddr transfer. figure 4?58 shows the stratix gx ioe structure. the ioe contains two input registers (plus a latch), two output registers, and two output enable registers. the desi gn can use both input registers and the latch to capture ddr input and both output registers to drive ddr outputs. additionally, the design can use the output enable (oe) register for fast clock-to-output enable timi ng. the negative edge-clocked oe register is used for ddr sdram interfacing. the quartus ii software automatically duplicates a single oe register that controls multiple output or bidirectional pins.
altera corporation 4?97 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?58. stratix gx ioe structure the ioes are located in i/o blocks ar ound the periphery of the stratix gx device. there are up to four ioes per row i/o block and six ioes per column i/o block. the row i/o blocks drive row, column, or direct link interconnects. the column i/o blocks drive column interconnects. figure 4?59 shows how a row i/o block connects to the logic array. figure 4?60 shows how a column i/o bloc k connects to th e logic array. dq output re g ister output a dq output re g ister output b input a input b dq oe re g ister oe dq oe re g ister dq input re g ister dq input re g ister dq input latch lo g ic array clk ena
4?98 altera corporation stratix gx device handbook, volume 1 february 2005 i/o structure figure 4?59. row i/o block c onnection to the interconnect notes to figure 4?59 : (1) the 16 control signals are composed of four output enables io_boe[3..0] , four clock enables io_bce[3..0] , four clocks io_clk[3..0] , and four clear signals io_bclr[3..0] . (2) the 28 data and control signals consist of eight data out lines: four lines each for ddr applications io_dataouta[3..0] and io_dataoutb[3..0] , four output enables io_coe[3..0] , four input clock enables io_cce_in[3..0] , four output clock enables io_cce_out[3..0] , four clocks io_cclk[3..0] , and four clear signals io_cclr[3..0] . 16 28 r4, r8 & r24 interconnects c4, c8 & c16 interconnects i/o block local interconnect 16 control signals from i/o interconnect (1) i/o interconnect 28 data & control signals from logic array (2) io_dataouta[3..0] io_dataoutb[3..0] io_clk[7:0] horizontal i/o block contains up to four ioes direct link interconnect to adjacent lab direct link interconnect to adjacent lab lab local interconnect lab horizontal i/o block
altera corporation 4?99 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?60. column i/o block connection to the interconnect notes to figure 4?60 : (1) the 16 control signals are composed of four output enables io_boe[3..0] , four clock enables io_bce[3..0] , four clocks io_bclk[3..0] , and four clear signals io_bclr[3..0] . (2) the 42 data and control signals consist of 12 data out lines; six lines each for ddr applications io_dataouta[5..0] and io_dataoutb[5..0] , six output enables io_coe[5..0] , six input clock enables io_cce_in[5..0] , six output clock enables io_cce_out[5..0] , six clocks io_cclk[5..0] , and six clear signals io_cclr[5..0] . 16 control signals from i/o interconnect (1) 42 data & control signals from logic array (2) vertical i/o block contains up to six ioes i/o block local interconnect i/o interconnec t io_datain[3:0] r4, r8 & r24 interconnects lab local interconnect c4, c8 & c16 interconnects 16 42 lab lab lab io_clk[7..0] vertical i/o block
4?100 altera corporation stratix gx device handbook, volume 1 february 2005 i/o structure stratix gx devices have an i/o interconnect similar to the r4 and c4 interconnect to drive high-fanout si gnals to and from the i/o blocks. there are 16 signals that drive into the i/o bloc ks composed of four output enables io_boe[3..0] , four clock enables io_bce[3..0] , four clocks io_bclk[3..0] , and four clear signals io_bclr[3..0] . the pin?s datain signals can drive the io interconnect, which in turn drives the logic array or other i/o blocks. in addition, the control and data signals can be driven from the logic array, providing a slower but more flexible routing resource. the row or column ioe clocks, io_clk[7..0] , provide a dedicated routing resource for low-skew, high-speed clocks. i/o clocks are generated from regional, global, or fast regional clocks (see ?plls & clock networks? on page 4?68 ). figure 4?61 illustrates the signal paths through the i/o block. figure 4?61. signal path through the i/o block each ioe contains its own control signal selection for the following control signals: oe , ce_in , ce_out , aclr/preset , sclr/preset , clk_in , and clk_out . figure 4?62 illustrates the control signal selection. row or column io_clk[7..0] io_boe[3..0] io_bce[3..0] io_bclk[3..0] io_bclr[3..0] io_datain0 io_datain1 io_dataout0 io_dataout1 io_coe oe ce_in ce_out io_cce_in aclr/preset io_cce_out sclr io_cclr clk_in io_cclk clk_out control si g nal selection ioe from i/o interconnect to logic array from logic array to other ioes
altera corporation 4?101 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?62. control signal selection per ioe in normal bidirectional operation, the input register can be used for input data requiring fast setup times. the input register can have its own clock input and clock enable separate from the oe and output registers. the output register can be used for da ta requiring fast clock-to-output performance. the oe register can be used for fast clock-to-output enable timing. the oe and output register share the same clock source and the same clock enable source from local interconnect in the associated lab, dedicated i/o clocks, and the column and row interconnects. figure 4?63 shows the ioe in bidirectional configuration. clk_out ce_in clk_in ce_out aclr/preset sclr/preset i/o interconnect [15..0] dedicated i/o clock [7..0] local interconnect local interconnect local interconnect local interconnect local interconnect oe io_coe io_cclr io_cce_out io_cce_in io_cclk io_bclk[3..0] io_bce[3..0] io_bclr[3..0] io_boe[3..0]
4?102 altera corporation stratix gx device handbook, volume 1 february 2005 i/o structure figure 4?63. stratix gx ioe in bidi rectional i/o configuration note (1) note to figure 4?63 : (1) all input signals to the io e can be inverted at the ioe. the stratix gx device ioe includes programmable delays that can be activated to ensure zero hold time s, input ioe register-to-logic array register transfers, or logic array-to-output ioe register transfers. a path in which a pin directly drives a register may require the delay to ensure zero hold time, whereas a path in which a pin drives a register through combinatorial logic may not require the delay. programmable delays exist for decreasing input-pin-to-logic-array and ioe input register delays. the quartus ii comp iler can program these delays to automatically mini mize setup time while prov iding a zero hold time. clrn/prn dq ena chip-wide reset oe register clrn/prn dq ena output register v ccio v ccio optional pci clamp programmable pull-up resistor column or row interconnect i/o interconnect [15..0] ioe_clk[7..0] bus-hold circuit output enable clock enable delay output clock enable delay logic array to output register delay output t zx delay oe register t co delay clrn/prn dq ena input register input clock enable delay input pin to input register delay input pin to logic array delay drive strength control open-drain output slew control sclr/preset oe clkout ce_out aclr/prn clkin ce_in output pin delay
altera corporation 4?103 february 2005 stratix gx device handbook, volume 1 stratix gx architecture programmable delays can increase the register-to-pin delays for output and/or output enable registers. a programmable delay exists to increase the t zx delay to the output pin, which is required for zbt interfaces. table 4?21 shows the programmable delays for stratix gx devices. the ioe registers in stratix gx devices share the same source for clear or preset. you can program preset or clea r for each individual ioe. you can also program the registers to power up high or low after configuration is complete. if programmed to power up low, an asynchronous clear can control the registers. if programmed to power up high, an asynchronous preset can control the registers. this feature prevents the inadvertent activation of another device?s acti ve-low input upon power-up. if one register in an ioe uses a preset or clear signal then all registers in the ioe must use that same signal if they require preset or clear. additionally, a synchronous reset signal is available for the ioe registers. double-data rate i/o pins stratix gx devices have six registers in the ioe, which support ddr interfacing by clocking data on both positive and negative clock edges. the ioes in stratix gx devices support ddr inputs, ddr outputs, and bidirectional ddr modes. table 4?21. stratix gx programmable delay chain programmable delays quartus ii logic option input pin to logic array delay decreas e input delay to internal cells input pin to input register delay de crease input delay to input register output pin delay increase delay to output pin output enable register t co delay increase delay to output enable pin output t zx delay increase t zx delay to output pin output clock enable delay increase output clock enable delay input clock enable delay increase input clock enable delay logic array to output register delay de crease input delay to output register output enable clock enable delay increase output enable clock enable delay
4?104 altera corporation stratix gx device handbook, volume 1 february 2005 i/o structure when using the ioe for ddr inputs, th e two input registers clock double rate input data on alternating edges. an input latch is also used within the ioe for ddr input acquisition. the la tch holds the data that is present during the clock high times. this allows both bits of data to be synchronous with the same clock ed ge (either rising or falling). figure 4?64 shows an ioe configured for ddr input. figure 4?65 shows the ddr input ti ming diagram. figure 4?64. stratix gx ioe in dd r input i/o configuration note (1) notes to figure 4?64 : (1) all input signals to the io e can be inverted at the ioe. (2) this signal connection is only al lowed on dedicated dq function pins. (3) this signal is for dedicated dqs function pins only. clrn/prn dq ena chip-wide reset input register clrn/prn dq ena input register vccio vccio optional pci clamp programmable pull-up resistor column or row interconnect i/o interconnect [15..0] dqs local bus (1), (2) to dqs local bus (3) ioe_clk[7..0] bus-hold circuit output clock enable delay clrn/prn dq ena latch input pin to input register delay sclr clkin aclr/prn (1) (1)
altera corporation 4?105 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?65. input timing diagram in ddr mode when using the ioe for ddr output s, the two output registers are configured to clock two data paths from les on rising clock edges. these output registers are multiplexed by the clock to drive the output pin at a 2 rate. one output register clocks the first bit out on the clock high time, while the other output register clocks the second bit out on the clock low time. figure 4?66 shows the ioe configured for ddr output. figure 4?67 shows the ddr output timing diagram. data at input pin a' b' clk a0 b1 a1 a1 b2 a2 a3 a2 a3 b1 b2 b3 b3 b4 input to logic array
4?106 altera corporation stratix gx device handbook, volume 1 february 2005 i/o structure figure 4?66. stratix gx ioe in dd r output i/o configuration notes (1) , (2) notes to figure 4?66 : (1) all input signals to the io e can be inverted at the ioe. (2) the tristate is by default active high. it can, however, be designed to be active low. clrn/prn dq ena chip-wide reset oe register clrn/prn dq ena oe register clrn/prn dq ena output register v ccio v ccio optional pci clamp programmabl e pull-up resistor column or row interconnect i/o interconnect [15..0] ioe_clk[7..0] bus-hold circuit logic array to output register delay output t zx delay oe register t co delay clrn/prn dq ena output register logic array to output register delay drive strength control open-drain output slew control used for ddr sdram clk sclr aclr/prn clkout output pin delay output enable clock enable delay output clock enable delay
altera corporation 4?107 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?67. output timing diagram in ddr mode the stratix gx ioe operates in bidirectional ddr mode by combining the ddr input and ddr output configurat ions. stratix gx device i/o pins transfer data on a ddr bidirectional bus to support ddr sdram. the negative-edge-clocked oe register hold s the oe signal inactive until the falling edge of the clock. this is done to meet ddr sdram timing requirements. external ram interfacing stratix gx devices support ddr sdram at up to 200 mhz (400-mbps data rate) through dedicated phas e-shift circuitry, qdr and qdrii sram interfaces up to 167 mhz, and zbt sram interfaces up to 200 mhz. stratix gx devices also provide preliminary support for reduced latency dram ii (rldram ii) at rates up to 200 mhz through the dedicated phase-shift circuitry. 1 in addition to the required si gnals for external memory interfacing, stratix gx devices of fer the optional clock enable signal. by default the quartus ii software sets the clock enable signal high, which tells the output register to update with new values. the output registers hold their own values if the design sets the clock enable signal low. see figure 4?63 . f to find out more about the ddr sd ram specification, see the jedec web site ( www.jedec.org ). for information on memory controller megafunctions for stratix gx devices, see the altera web site ( www.altera.com ). see an 342: interfacing ddr sdram with stratix & stratix gx devices for more information on ddr sdram interface in stratix gx. also see an 349: qdr sram controll er reference design for stratix & stratix gx devices and an 329: zbt sram controller reference design for stratix & stratix gx devices . f r o m in ter n a l reg i sters ddr output clk a b b1 a1 b2 a2 b3 a3 a2 a1 a3 a4 b1 b2 b3 b4
4?108 altera corporation stratix gx device handbook, volume 1 february 2005 i/o structure table 4?22 shows the performance specification for ddr sdram, rldram ii, qdr sram, qdrii sram, and zbt sram interfaces in ep1sgx10 through ep1sgx40 devices. the ddr sdram and qdr sram numbers in table 4?22 have been verified with hardware characterization with third-party ddr sdram and qdr sram devices over temperature and voltage extremes. in addition to six i/o registers and one input latch in the ioe for interfacing to these high-speed memo ry interfaces, stratix gx devices also have dedicated circuitry for in terfacing with ddr sdram. in every stratix gx device, the i/o banks at the top (i/o banks 3 and 4) and bottom (i/o banks 7 and 8) of the device support ddr sdram up to 200 mhz. these pins support dqs signals with dq bus modes of 8, 16, or 32. table 4?22. external ram support in ep1sgx10 through ep1sgx40 devices ddr memory type i/o standard maximum clock rate (mhz) -5 speed grade -6 speed grade -7 speed grade ddr sdram (1) , (2) sstl-2 200 167 133 ddr sdram - side banks (2) , (3) , (4) sstl-2 150 133 133 rldram ii (4) 1.8-v hstl 200 (5) (5) qdr sram (6) 1.5-v hstl 167 167 133 qdrii sram (6) 1.5-v hstl 200 167 133 zbt sram (7) lvttl 200 200 167 notes to table 4?22 : (1) these maximum clock rates apply if the stratix gx device uses dqs phase-shift circuitry to interface with ddr sdram. dqs phase-shift circuitry is only available in the top and bottom i/o banks (i/o banks 3, 4, 7, and 8). (2) for more informati on on ddr sdram, see an 342: interfacing ddr sdram wi th stratix & stratix gx devices. (3) ddr sdram is supported on the stratix gx device side i/o banks (i/o banks 1, 2, 5, and 6) without dedicated dqs phase-shift circuitry. the read dqs signal is ignored in this mode. (4) these performance specifications are preliminary. (5) this device does not support rldram ii. (6) for more information on qdr or qdrii sram, see an 349: q dr sram controller reference design for stratix & stratix gx devices . (7) for more informati on on zbt sram, see an 329: zbt sram controller reference design for stratix & stratix gx devices .
altera corporation 4?109 february 2005 stratix gx device handbook, volume 1 stratix gx architecture table 4?23 shows the number of dq and dqs buses that are supported per device. a compensated delay element on ea ch dqs pin automatically aligns input dqs synchronization signals with the data window of their corresponding dq data signals. the dqs signals drive a local dqs bus in the top and bottom i/o banks. this dq s bus is an additional resource to the i/o clocks and clocks dq inpu t registers with the dqs signal. two separate single phase-shifting reference circuits are located on the top and bottom of the stratix gx device. each circuit is driven by a system reference clock through the clk pins that is the same frequency as the dqs signal. clock pins clk[15..12]p feed the phase-shift circuitry on the top of the device and clock pins clk[7..4]p feed the phase-shift circuitry on the bottom of the device . the phase-shifting reference circuit on the top of the device controls th e compensated delay elements for all 10 dqs pins located at the top of the device. the phase-shifting reference circuit on the bottom of the device controls the compensated delay elements for all 10 dqs pins locate d on the bottom of the device. all 10 delay elements (dqs signals) on ei ther the top or bottom of the device shift by the same degree amount. for example, all 10 dqs pins on the top of the device can be shifted by 90 an d all 10 dqs pins on the bottom of the device can be shifted by 72. the reference circuits require a maximum of 256 system reference clock cycles to set the correct phase on the dqs delay elements. figure 4?68 illustrates the phase-shift reference circuit control of each dqs delay shift on the top of the device. this same circuit is duplicated on the bottom of the device. table 4?23. dqs & dq bus mode support note (1) device package number of 8 groups number of 16 groups number of 32 groups ep1sgx10 672-pin fineline bga 12 (2) 00 ep1sgx25 672-pin fineline bga 16 (3) 84 1,020-pin fineline bga 20 8 4 ep1sgx40 1,020-pin fineline bga 20 8 4 notes to table 4?23 : (1) see the selectable i/o standards in stratix & stratix gx devices chapter of the stratix gx device handbook, volume 2 for v ref guidelines. (2) these packages have six groups in i/o banks 3 and 4 and six groups in i/o banks 7 and 8. (3) these packages have eight grou ps in i/o banks 3 and 4 and eigh t groups in i/o banks 7 and 8.
4?110 altera corporation stratix gx device handbook, volume 1 february 2005 i/o structure figure 4?68. simplified diagram of the dqs phase-shift circuitry see the external memory interfaces chapter of the stratix gx device handbook, volume 2 for more information on external memory interfaces. programmable drive strength the output buffer for each stratix gx device i/o pin has a programmable drive strength control for certain i/o standards. the lvttl and lvcmos standard has several levels of drive strength that the user can control. sstl-3 class i and ii, sstl-2 class i and ii, hstl class i and ii, and 3.3-v gtl+ support a minimum setting, the lowest drive strength that guarantees the i oh /i ol of the standard. using minimum settings provides signal slew rate control to reduce system noise and signal overshoot. phase comparator up/down counter delay chains input reference clock control si g nals to dqs pins 6
altera corporation 4?111 february 2005 stratix gx device handbook, volume 1 stratix gx architecture table 4?24 shows the possible settings fo r the i/o standards with drive strength control. the quartus ii software, beginning wi th version 4.2, reports current strength as ?pci compliant? for 3.3- v pci, 3.3-v pci-x 1.0, and compact pci i/o standards. stratix gx devices support series on-chip termination (oct) using programmable drive strength. for more information, contact your altera support representative. open-drain output stratix gx devices provide an option al open-drain (e quivalent to an open-collector) output for each i/o pi n. this open-drain output enables the device to provide system-level co ntrol signals (that is, interrupt and write-enable signals) that can be asserted by any of several devices. table 4?24. programmable drive strength i/o standard i oh / i ol current strength setting (ma) 3.3-v lvttl 24 (1) , 16, 12, 8, 4 3.3-v lvcmos 24 (2) , 12 (1) , 8, 4, 2 2.5-v lvttl/lvcmos 16 (1) , 12, 8, 2 1.8-v lvttl/lvcmos 12 (1) , 8, 2 1.5-v lvcmos 8 (1) , 4, 2 gtl/gtl+ 1.5-v hstl class i and ii 1.8-v hstl class i and ii sstl-3 class i and ii sstl-2 class i and ii sstl-18 class i and ii support maximum and minimum strength notes to ta b l e 4 ? 2 4 : (1) this is the quartus ii soft ware default current setting. (2) i/o banks 1 and 2 do not support this setting.
4?112 altera corporation stratix gx device handbook, volume 1 february 2005 i/o structure slew-rate control the output buffer for each stratix gx device i/o pin has a programmable output slew-rate control that can be configured for low-noise or high- speed performance. a faster slew rate provides high-speed transitions for high-performance systems. howeve r, these fast transitions may introduce noise transien ts into the system. a slow slew rate reduces system noise, but adds a nominal delay to rising and falling edges. each i/o pin has an individual slew-rate control, allowing you to specify the slew rate on a pin-by-pin basis. the slew-rate control affects both the rising and falling edges. bus hold each stratix gx device i/o pin provid es an optional bus-hold feature. the bus-hold circuitry can weakly hold the signal on an i/ o pin at its last- driven state. since the bus-hold feature holds the last-driven state of the pin until the next input si gnal is present, an exte rnal pull-up or pull-down resistor is not needed to hold a sign al level when the bus is tri-stated. table 4?25 shows bus hold support for different pin types. the bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. you can select this featur e individually for each i/o pin. the bus-hold output drives no higher than v ccio to prevent overdriving signals. if the bus-hold feature is enabled, the programmable pull-up option cannot be used. disable the bus-hold feature when using open- drain outputs with the gtl+ i/o standard or when the i/o pin has been configured for differential signals. table 4?25. bus hold support pin type bus hold i/o pins v clk[15..0] clk[0,1,2,3,8,9,10,11] fclk v fpll[7..10]clk
altera corporation 4?113 february 2005 stratix gx device handbook, volume 1 stratix gx architecture the bus-hold circuitry uses a resistor with a nominal resistance (r bh ) of approximately 7 k to weakly pull the signal level to the last-driven state. the chapter dc & switching characteristics of the stratix gx device handbook, volume 1 gives the specific sustaining current driven through this resistor and the overdrive curren t used to identify the next-driven input level. this information is provided for each v ccio voltage level. the bus-hold circuitry is active only after configuration. when going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration. programmable pull-up resistor each stratix gx device i/o pin provides an optional programmable pull- up resistor during user mode. if this feature is enabled for an i/o pin, the pull-up resistor (typically 25 k ) weakly holds the output to the v ccio level of the output pin?s bank. table 4?26 shows which pin types support the weak pull-up resistor feature. advanced i/o standard support stratix gx device ioes support the following i/o standards: lvttl lvcmos 1.5 v 1.8 v 2.5 v 3.3-v pci 3.3-v pci-x 1.0 3.3-v agp (1 and 2 ) table 4?26. programmable weak pull-up resistor support pin type programmable w eak pull-up resistor i/o pins v clk[15..0] fclk v fpll[7..10]clk configuration pins jtag pins v (1) note to table 4?26 : (1) tdo pins do not support programmable weak pull-up resistors.
4?114 altera corporation stratix gx device handbook, volume 1 february 2005 i/o structure lvds lvpecl 3.3-v pcml hypertransport differential hstl (on input/output clocks only) differential sstl (on output column clock pins only) gtl/gtl+ 1.5-v hstl class i and ii 1.8-v hstl class i and ii sstl-3 class i and ii sstl-2 class i and ii sstl-18 class i and ii ctt table 4?27 describes the i/o standards supported by stratix gx devices. table 4?27. stratix gx support ed i/o standards (part 1 of 2) i/o standard type input reference voltage (v ref ) (v) output supply voltage (v ccio ) (v) board termination voltage (v tt ) (v) lvttl single-ended n/a 3.3 n/a lvcmos single-ended n/a 3.3 n/a 2.5 v single-ended n/a 2.5 n/a 1.8 v single-ended n/a 1.8 n/a 1.5 v single-ended n/a 1.5 n/a 3.3-v pci single-ended n/a 3.3 n/a 3.3-v pci-x 1.0 single-ended n/a 3.3 n/a lvds differential n/a 3.3 n/a lvpecl differential n/a 3.3 n/a 3.3-v pcml differential n/a 3.3 n/a hypertransport differential n/a 2.5 n/a differential hstl (1) differential 0.75 1.5 0.75 differential sstl (2) differential 1.25 2.5 1.25 gtl voltage-referenced 0.8 n/a 1.20 gtl+ voltage-referenced 1.0 n/a 1.5 1.5-v hstl class i and ii voltage-referenced 0.75 1.5 0.75 1.8-v hstl class i and ii voltage-referenced 0.9 1.8 0.9 sstl-18 class i and ii voltage-referenced 0.90 1.8 0.90 sstl-2 class i and ii voltage-referenced 1.25 2.5 1.25
altera corporation 4?115 february 2005 stratix gx device handbook, volume 1 stratix gx architecture f for more information on i/o st andards supported by stratix gx devices, see the selectable i/o standards in stratix & stratix gx devices chapter of the stratix gx device handbook, volume 2 . stratix gx devices contain eight i/o banks in addition to the four enhanced pll external cloc k out banks, as shown in figure 4?69 . the four i/o banks on the right and left of th e device contain circuitry to support high-speed differential i/o fo r lvds, lvpecl, 3.3-v pcml, and hypertransport inputs and output s. these banks support all i/o standards listed in table 4?27 except pci i/o pins or pci-x 1.0, gtl, sstl-18 class ii, and hstl class ii outputs. the top and bottom i/o banks support all single-ended i/o standards. additionally, stratix gx devices support four enhanced pll external clock output banks, allowing clock output capabilities su ch as differential support for sstl and hstl. table 4?28 shows i/o standard support for each i/o bank. sstl-3 class i and ii voltage-referenced 1.5 3.3 1.5 agp (1 and 2 ) voltage-referenced 1.32 3.3 n/a ctt voltage-referenced 1.5 3.3 1.5 notes to table 4?27 : (1) this i/o standard is only availa ble on input and output clock pins. (2) this i/o standard is only avai lable on output column clock pins. table 4?27. stratix gx support ed i/o standards (part 2 of 2) i/o standard type input reference voltage (v ref ) (v) output supply voltage (v ccio ) (v) board termination voltage (v tt ) (v)
4?116 altera corporation stratix gx device handbook, volume 1 february 2005 i/o structure figure 4?69. strati x gx i/o banks notes (1) , (2) , (3) notes to figure 4?69 : (1) figure 4?69 is a top view of the stratix gx silicon die. (2) banks 9 through 12 are enhanced pll external clock output banks. (3) if the high-speed differential i/o pins are not used for high-speed differential signaling, they can support all of the i/o standards except hstl class i and ii, gtl, sstl-18 class ii, pci, pci-x, and agp 1/2. (4) for guidelines for placing single-ended i/o pads next to differential i/o pads, see the selectable i/o standards in stratix & stratix gx devices chapter in the stratix gx device handbook, volume 2 . (5) these i/o banks in stratix gx device s also support the lvds, lvpecl, and 3. 3-v pcml i/o standards on reference clocks and receiver input pins (ac coupled) lvds, lvpecl, 3.3-v pcml, and hypertransport i/o block and regular i/o pins (3) i/o banks 3, 4, 9 & 10 support all single-ended i/o standards (2) i/o banks 7, 8, 11 & 12 support all single-ended i/o standards (2) i/o banks 1 and 2 support all single-ended i/o standards except differential hstl output clocks, differential sstl-2 output clocks, hstl class ii, gtl, sstl-18 class ii, pci, pci-x, and agp 1 /2 dqst9 dqst8 dqst7 dqst6 dqst5 dqst4 dqst3 dqst2 dqst1 dqst0 pll5 vref1b3 vref2b3 vref3b3 vref4b3 vref5b3 vref1b4 vref2b4 vref3b4 vref4b4 vref5b4 vref5b8 vref4b8 vref3b8 vref2b8 vref1b8 vref5b7 vref4b7 vref3b7 vref2b7 vref1b7 pll6 dqsb9 dqsb8 dqsb7 dqsb6 dqsb5 dqsb4 dqsb3 dqsb2 dqsb1 dqsb0 910 vref1b2 vref2b2 vref3b2 vref4b2 vref1b1 vref2b1 vref3b1 vref4b1 pll1 pll2 bank 1 bank 2 bank 3 bank 4 11 12 bank 8 bank 7 lvds, lvpecl, 3.3-v pcml, and hypertransport i/o block and regular i/o pins (3) pll7 pll8 pll12 pll11 (4) (4) i/o bank 13 (5) i/o bank 14 (5) i/o bank 17 (5) i/o bank 16 (5) i/o bank 15 (5) 1.5-v pcml (5)
altera corporation 4?117 february 2005 stratix gx device handbook, volume 1 stratix gx architecture table 4?28 shows i/o standard support for each i/o bank. table 4?28. i/o support by bank (part 1 of 2) i/o standard top & bottom banks (3, 4, 7 & 8) left banks (1 & 2) enhanced pll external clock output banks (9, 10, 11 & 12) lv t t l vvv lv c m o s vvv 2.5 v vvv 1.8 v vvv 1.5 v vvv 3.3-v pci vv 3.3-v pci-x 1.0 vv lvpecl vv 3.3-v pcml vv lv d s vv hypertransport technology vv differential hstl (clock inputs) vv differential hstl (clock outputs) v differential sstl (clock outputs) v 3.3-v gtl vv 3.3-v gtl+ vvv 1.5-v hstl class i vvv 1.5-v hstl class ii vv 1.8-v hstl class i vvv 1.8-v hstl class ii vv sstl-18 class i vvv sstl-18 class ii vv sstl-2 class i vvv sstl-2 class ii vvv sstl-3 class i vvv
4?118 altera corporation stratix gx device handbook, volume 1 february 2005 i/o structure each i/o bank has its own vccio pins. a single device can support 1.5-, 1.8-, 2.5-, and 3.3-v interfaces; each bank can support a different standard independently. each ba nk also has dedicated vref pins to support any one of the voltage-referenced standa rds (such as sstl-3) independently. each i/o bank can support multiple standards with the same v ccio for input and output pins. each bank can support one voltage-referenced i/o standard. for example, when v ccio is 3.3 v, a bank can support lvttl, lvcmos, 3.3-v pci, and sstl-3 for inputs and outputs. differential on-chip termination stratix gx devices provide differenti al on-chip termination (lvds i/o standard) to reduce reflections and main tain signal integrity. differential on-chip termination simplifies board design by minimizing the number of external termination resistors re quired. termination can be placed inside the package, eliminating sm all stubs that can still lead to reflections. the internal termination is designed using transistors in the linear region of operation. stratix gx devices support internal differential termination with a nominal resistance value of 137.5 for lvds input receiver buffers. lvpecl signals require an external termination resistor. figure 4?70 shows the device with differential termination. sstl-3 class ii vvv agp (1 and 2 ) vv ctt vvv table 4?28. i/o support by bank (part 2 of 2) i/o standard top & bottom banks (3, 4, 7 & 8) left banks (1 & 2) enhanced pll external clock output banks (9, 10, 11 & 12)
altera corporation 4?119 february 2005 stratix gx device handbook, volume 1 stratix gx architecture figure 4?70. lvds input differ ential on-chip termination i/o banks on the left and right side of the device support lvds receiver (far-end) differential termination. table 4?29 shows the stratix gx device di fferential termination support. table 4?30 shows the termination support for different pin types. the differential on-chip resistance at the receiver input buffer is 118 20 %. r d + e + e transmitting device receiving device with differential termination z 0 z 0 table 4?29. differential terminat ion supported by i/o banks differential termination support i/o standard support top & bottom banks (3, 4, 7 & 8) left banks (1 & 2) differential termination (1) , (2) lv d s v notes to table 4?29 : (1) clock pin clk0 , clk2 , clk9 , clk11 , and pins fpll[7..10]clk do not support differential termination. (2) differential termination is only su pported for lvds because of a 3.3-v v ccio . table 4?30. differential termination support across pin types pin type r d top and bottom i/o banks (3, 4, 7, and 8) diffio_rx[] v clk[0,2,9,11],clk[4-7],clk[12-15] clk[1,3,8,10] v fclk fpll[7..10]clk
4?120 altera corporation stratix gx device handbook, volume 1 february 2005 i/o structure however, there is additional resistan ce present between the device ball and the input of the receiver buffer, as shown in figure 4?71 . this resistance is because of package trace resistance (which can be calculated as the resistance from the package ball to the pad) and the parasitic layout metal routing resistance (which is shown between the pad and the intersection of the on-chip termination and input buffer). figure 4?71. differential resistance of lvds differential pin pair (r d ) table 4?31 defines the specification for internal termination resistance for commercial devices. multivolt i/o interface the stratix gx architecture supports th e multivolt i/o interface feature, which allows stratix gx devices in all packages to interface with systems of different supply voltages. the stratix gx vccint pins must always be connected to a 1.5-v power supply. with a 1.5-v v ccint level, input pins are 1.5-v, 1.8-v, 2.5-v, and 3.3-v tolerant. the vccio pins can be connected to either a 1.5-v, 1.8-v, lvds input buffer differential on-chip termination resisto r 9.3 9.3 0.3 0.3 r d pad package ball package ball pad table 4?31. differential on-chip termination symbol description conditions resistance unit min typ max r d (2) internal differential termination for lvds commercial (1) , (3) 110 135 165 industrial (2) , (3) 100 135 170 notes to table 4?31 : (1) data measured over minimum conditions (t j = 0 c, v ccio +5%) and maximum conditions (t j = 85 c, v ccio =?5%). (2) data measured over minimum conditions (t j = ?40 c, v ccio +5%) and maximum conditions (t j = 100 c, v ccio =?5%). (3) lvds data rate is supported for 840 mbps using internal differential termination.
altera corporation 4?121 february 2005 stratix gx device handbook, volume 1 stratix gx architecture 2.5-v, or 3.3-v power supply, depe nding on the output requirements. the output levels are compatible with systems of the same voltage as the power supply (for example, when vccio pins are connected to a 1.5-v power supply, the output levels ar e compatible with 1.5-v systems). when vccio pins are connected to a 3.3-v power supply, the output high is 3.3 v and is compatible wi th 3.3-v or 5.0-v systems. table 4?32 summarizes stratix gx multivolt i/o support. power sequencing & hot socketing because stratix gx devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. therefore, the vccio and vccint power supplies may be powered in any order. signals can be driven into stratix gx devices before and during power up without damaging the device. in ad dition, stratix gx devices do not drive out during power up. once operating conditions are reached and the device is configured, stratix gx devices operate as specified by the user. for more information, see the selectable i/o standards in stratix & stratix gx devices chapter of the stratix gx device handbook, volume 2 . table 4?32. stratix gx multivolt i/o support note (1) v ccio (v) input signal (5) output signal (6) 1.5 v1.8 v2.5 v3.3 v5.0 v1.5 v1.8 v2.5 v3.3 v5.0 v 1.5 vv v (2) v (2) v 1.8 v (2) v v (2) v (2) v (3) v 2.5 vv v (3) v (3) v 3.3 v (2) v v (4) v (3) v (3) v (3) vv notes to table 4?32 : (1) to drive inputs higher than v ccio but less than 4.1 v, disable the pci clamping diode. however, to drive 5.0-v inputs to the device, enable the pci clamping diode to prevent v i from rising above 4.0 v. (2) the input pin current may be slightly higher than the typical value. (3) although v ccio specifies the voltage necessary for the stratix gx device to drive out, a receiving device powered at a different level can still interface with the stra tix gx device if it has inputs that tolerate the v ccio value. (4) stratix gx devices can be 5.0-v tolera nt with the use of an external resistor and the internal pci clamp diode. (5) this is the external signal that is driving the stratix gx device. (6) this represents the system voltage that stratix gx support s when a vccio pin is connected to a specific voltage level. for example, when vccio is 3.3 v and if the i/o st andard is lvttl/lvcmos, the output high of the signal coming out from stratix gx is 3.3 v and is compatible with 3.3-v or 5.0-v systems.
4?122 altera corporation stratix gx device handbook, volume 1 february 2005 ieee std. 1149.1 (jtag) boundary-scan support ieee std. 1149.1 (jtag) boundary-scan support all stratix gx devices provide jtag bst circuitry that complies with the ieee std. 1149.1a-1990 spec ification. jtag boundary-scan testing can be performed either before or after, but not during configuration. stratix gx devices can also use the jtag port fo r configuration together with either the quartus ii software or hardware using either jam files ( .jam ) or jam byte-code files ( .jbc ). stratix gx devices support ioe i/o standard setting reconfiguration through the jtag bst chain. the jtag chain can update the i/o standard for all input and output pins any time before or during user mode. you can use this ability for jtag testing before configuration when some of the stratix gx pins drive or receive from other devices on the board using voltage-referenced standards. because the stratix gx device may not be configured before jtag testing, the i/o pins may not be configured for appropriate electrical standards for chip-to-chip communication. programming those i/o standards via jtag allows you to fully test i/o connection to other devices. the enhanced pll reconfig uration bits are part of the jtag chain before configuration and after power-up. after device configuration, the pll reconfiguration bits are not part of the jtag chain. stratix gx devices also use the jtag port to monitor the logic operation of the device with the signaltap ? embedded logic analyzer. stratix gx devices support the jtag instructions shown in table 4?33 . table 4?33. stratix gx jtag instructions (part 1 of 2) jtag instruction description sample/preload allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. also used by the signaltap ? embedded logic analyzer. extest (1) allows the external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. bypass places the 1-bit bypas s register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation. usercode selects the 32-bit usercode register and places it between the tdi and tdo pins, allowing the usercode to be serially shifted out of tdo . idcode selects the idcode register and places it between tdi and tdo , allowing the idcode to be serially shifted out of tdo . highz (1) places the 1-bit bypas s register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the i/o pins.
altera corporation 4?123 february 2005 stratix gx device handbook, volume 1 stratix gx architecture the stratix gx device instruction register length is 10 bits, and the usercode register length is 32 bits. tables 4?34 and 4?35 show the boundary-scan register length and idcode information for stratix gx devices. clamp (1) places the 1-bit bypas s register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation while holding i/o pins to a state defined by the data in the boundary-scan register. icr instructions used when configuring a stratix gx device th rough the jtag port with a masterblaster tm or byteblastermv tm download cable, or when using a .jam file or .jbc file with an embedded processor. pulse_nconfig emulates pulsing the nconfig pin low to trigger reconfiguration even though the physical pin is unaffected. config_io allows the ioe standards to be configured thro ugh the jtag chain. stops configuration if executed during configuration. can be executed before or after configuration. signaltap instructions monitors internal device operation with the signaltap embedded logic analyzer. note to table 4?33 : (1) bus hold and weak pull-up resistor feat ures override the high-impedance state of highz , clamp , and extest . table 4?33. stratix gx jtag instructions (part 2 of 2) jtag instruction description table 4?34. stratix gx boundary-scan register length device boundary-scan register length ep1sgx10 1,029 ep1sgx25 1,665 ep1sgx40 1,941 table 4?35. 32-bit stratix gx device idcode (part 1 of 2) device idcode (32 bits) (1) version (4 bits) part number (16 bits) manufacturer identity (11 bits) lsb (1 bit) (2) ep1sgx10 0000 0010 0000 0100 0001 000 0110 1110 1 ep1sgx25 0000 0010 0000 0100 0011 000 0110 1110 1
4?124 altera corporation stratix gx device handbook, volume 1 february 2005 ieee std. 1149.1 (jtag) boundary-scan support figure 4?72 shows the timing requirements for the jtag signals. figure 4?72. stratix gx jtag waveforms table 4?36 shows the jtag timing parame ters and values for stratix gx devices. ep1sgx40 0000 0010 0000 0100 0101 000 0110 1110 1 notes to table 4?35 : (1) the most significant bit (msb) is at the left end of the string. (2) the idcode?s least significant bit (lsb) is always 1 . table 4?35. 32-bit stratix gx device idcode (part 2 of 2) device idcode (32 bits) (1) version (4 bits) part number (16 bits) manufacturer identity (11 bits) lsb (1 bit) (2) table 4?36. stratix gx jtag timing parameters & values (part 1 of 2) symbol parameter min (ns) max (ns) t jcp tck clock period 100 t jch tck clock high time 50 t jcl tck clock low time 50 t jpsu jtag port setup time 20 tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms si g nal to be captured si g nal to be driven t jszx t jssu t jsh t jsco t jsxz
altera corporation 4?125 february 2005 stratix gx device handbook, volume 1 stratix gx architecture t jph jtag port hold time 45 t jpco jtag port clock to output 25 t jpzx jtag port high impedance to valid output 25 t jpxz jtag port valid output to high impedance 25 t jssu capture register setup time 20 t jsh capture register hold time 45 t jsco update register clock to output 35 t jszx update register high impedance to valid output 35 t jsxz update register valid output to high impedance 35 table 4?36. stratix gx jtag timing parameters & values (part 2 of 2) symbol parameter min (ns) max (ns)
4?126 altera corporation stratix gx device handbook, volume 1 february 2005 ieee std. 1149.1 (jtag) boundary-scan support
altera corporation 5?1 february 2005 5. configuration & testing signaltap embedded logic analyzer stratix ? gx devices feature the signaltap ? embedded logic analyzer, which monitors design operation over a period of time through the ieee std. 1149.1 (jtag) circuitry. you can analyze internal logic at speed without bringing intern al signals to the i/o pi ns. this feature is particularly important for advanced packages, such as fineline bga ? packages, because it can be difficul t to add a connection to a pin during the debugging process after a board is designed and manufactured. configuration the logic, circuitry, and interconnect s in the stratix gx architecture are configured with cmos sram elements. stratix gx devices are reconfigurable and are 100 % tested prior to shipment. as a result, you do not have to generate test vectors for fault coverage purposes, and can instead focus on simulation and design verification. in addition, you do not need to manage inventories of different asic designs. stratix gx devices can be configured on the board for the specific functionality required. stratix gx devices are configured at sy stem power-up with data stored in an altera serial configuration device or provided by a system controller. altera offers in-system programmabi lity (isp)-capable configuration devices that configure stratix gx devices via a serial data stream. stratix gx devices can be configured in under 100 ms using 8-bit parallel data at 100 mhz. the stratix gx devi ce?s optimized interface allows microprocessors to configure it serially or in parallel, and synchr onously or asynchronously. the interface also enables microprocessors to treat stratix gx devices as memory and configure them by writing to a virtual memory location, making reconfigurat ion easy. after a stratix gx device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. real-time changes can be made during system operation, enabling innovative reconfigurable computing applications. operating modes the stratix gx architecture uses sr am configuration elements that require configuration data to be loaded each time the circuit powers up. the process of physically loading the sram data into the device is called configuration. during initialization, which occurs immediately after configuration, the device resets regist ers, enables i/o pins, and begins to operate as a logic device. the i/o pins are tri-stated during power up, sgx51005-1.0
5?2 altera corporation stratix gx device handbook, volume 1 february 2005 configuration and before and during configuration. together, the configuration and initialization processes are called command mode. normal device operation is called user mode. a built-in weak pull-up resistor pulls all user i/o pins to v ccio before and during device configuration. sram configuration elements allow stratix gx devices to be reconfigured in-circuit by loading new configuration data into the device. with real-time reconfiguration, the device is forced into command mode with a device pin. the configuration process loads different configuration data, reinitializes the device, and resumes user-mode operation. you can perform in-field upgrades by distribu ting new configuration files either within the system or remotely. configuration schemes you can load the configuration data for a stratix gx device with one of five configuration schemes (see table 5?1 ), chosen on the basis of the target application. you can use a configuration device, intelligent controller, or the jtag port to configure a stratix gx device. a configuration device can automatically configure a stratix gx device at system power-up. you can configure multiple stratix gx devices in any of five configuration schemes by connect ing the configuration enable ( nce ) and configuration enable output ( nceo ) pins on each device. table 5?1. data sources for configuration configuration scheme data source configuration device enhanced or epc2 configuration device passive serial (ps) byteblastermv? or masterblaster? download cable or serial data source passive parallel asynchronous (ppa) parallel data source fast passive parallel parallel data source jtag masterblaster or byteblastermv download cable or a microprocessor with a jam or jbc file (.jam or .jbc)
altera corporation 5?3 february 2005 stratix gx device handbook, volume 1 configuration & testing partial reconfiguration the enhanced plls within the stratix gx device family support partial reconfiguration of their multiply, di vide, and time delay settings without reconfiguring the entire device. you ca n use either serial data from the logic array or regular i/o pins to pr ogram the pll?s counter settings in a serial chain. this option provides considerable flexibility for frequency synthesis, allowing real-time variat ion of the pll frequency and delay. the rest of the device is functional while reconfiguring the pll. see the stratix gx architecture chapter of the stratix gx device handbook , volume 1 for more information on stratix gx plls. remote update co nfiguration modes stratix gx devices also support remote configuration using an altera enhanced configuration device (for example, epc16, epc8, and epc4 devices) with page mode selection. factory configuration data is stored in the default page of the configurat ion device. this is the default configuration which contains the design required to control remote updates and handle or recover fr om errors. you write the factory configuration once into the flash memory or configuration device. remote update data can update any of the remaining pages of the configuration device. if there is an er ror or corruption in a remote update configuration, the configuration device reverts back to the factory configuration information. there are two remote configuration modes: remote and local configuration. you can use the remote update configuration mode for all three configuration modes: serial, pa rallel synchronou s, and parallel asynchronous. configuration devices (for example, epc16 devices) only support serial and parallel synchron ous modes. asynchronous parallel mode allows remote updates when an intelligent host is used to configure the stratix gx device. this host must support page mode settings similar to an epc16 device. remote update mode when the stratix gx device is first powered-up in remote update programming mode, it loads the configuration located at page address 000 . the factory configuration should always be located at page address 000 , and should never be remotely updated. the factory configuration contains the requir ed logic to perform the following operations: determine the page address/load lo cation for the next application?s configuration data recover from a previous configuration error
5?4 altera corporation stratix gx device handbook, volume 1 february 2005 configuration receive new configuration data and write it into the configuration device the factory configuration is the defa ult and takes control if an error occurs while loading the application configuration. while in the factory configuration, the factory-configuration logic performs the following operations: loads a remote update-control register to determine the page address of the new application configuration determines whether to enable a user watchdog timer for the application configuration determines what the watchdog time r setting should be if it is enabled the user watchdog timer is a coun ter that must be continually reset within a specific amount of time in the user mode of an application configuration to ensure that valid configuration occurred during a remote update. only valid application configurations designed for remote update can reset the user watchdog timer in user mode. if a valid application configuration does not re set the user watchdog timer in a specific amount of time, the timer up dates a status register and loads the factory configuration. the user watchd og timer is automatically disabled for factory configurations. if an error occurs in loading th e application configuration, the configuration logic writes a status register to specify the cause of the reconfiguration. once this occurs, the stratix gx device automatically loads the factory configuration, wh ich reads the status register and determines the reason for reconfig uration. based on the reason, the factory configuration takes appropriate steps and writes the remote update control register to specify th e next application configuration page to be loaded. when the stratix gx device succ essfully loads the application configuration, it enters into user mode. the stratix gx device then executes the main application of the user. intellectual property (ip), such as a nios ? embedded processor, can help the stratix gx device determine when remote update is coming. the nios embedded pr ocessor or user logic receives incoming data, writes it to the configuration device, and loads the factory configuration. th e factory configuration reads the remote update status register and determine the valid application configuration to load. figure 5?1 shows the stratix gx remote update. figure 5?2 shows the transition diagram for remote update mode.
altera corporation 5?5 february 2005 stratix gx device handbook, volume 1 configuration & testing figure 5?1. stratix gx de vice remote update note to figure 5?1 : (1) when the stratix gx device is configured with the factor y configuration, it can handle update data from epc16, epc8, or epc4 configuration device pages and poin t to the next page in the configuration device. watchdo g timer stratix gx device new remote confi g uration data confi g uration device application confi g uration application confi g uration factory confi g uration (1) configuration device updates stratix gx device with factory configuration (to handle update) or new application configuration page 7 page 6 page 0
5?6 altera corporation stratix gx device handbook, volume 1 february 2005 configuration figure 5?2. remote update transition diagram notes (1) , (2) notes to figure 5?2 : (1) remote update of application configura tion is controlled by a nios embedded processor or user logic programmed in the factory or application configurations. (2) up to seven pages can be specified allowing up to seven different configuration applications. confi g uration error confi g uration error application 1 confi g uration confi g uration error factory confi g uration reload an application reload an application application n confi g uration power-up
altera corporation 5?7 february 2005 stratix gx device handbook, volume 1 configuration & testing local update mode local update mode is a simplified version of the remote update. this feature is intended for simple systems that need to load a single application configuration immediatel y upon power-up without loading the factory configuration first. local update designs have only one application configuratio n to load, so it does not require a factory configuration to determine which application configuration to use. figure 5?3 shows the transition diagram for local update mode. figure 5?3. local update transition diagram stratix gx automated single event upset (seu) detection stratix gx devices offer on-chip circ uitry for automated checking of single event upset (seu) detection. some applications that require the device to operate error free at high elevations or in close proximity to earth?s north or south pole require periodic checks to ensure continued data integrity. the error detection cyclic redundancy code (crc) feature controlled by the device & pin options dialog box in the quartus ii software uses a 32-bit crc circuit to en sure data reliability and is one of the best options for mitigating seu. nconfig nconfig confi g uration error application confi g uration confi g uration error factory confi g uration power-up or nconfig
5?8 altera corporation stratix gx device handbook, volume 1 february 2005 temperature-sensing diode you can implement the error detection crc feature with existing circuitry in stratix gx devices, eliminating the need for external logic. for stratix gx devices, the crc is comp uted by quartus ii and downloaded into the device as a part of the configuration bit stream. the crc_error pin reports a soft error when configuration sram data is corrupted, triggering device reconfiguration. custom-built circuitry dedicated circuitry is built into st ratix gx devices to perform error detection automatically. this error de tection circuitry constantly checks for errors in the configuration sram cells while the device is in user mode. you can monitor one external pin for the error and use it to trigger a reconfiguration cycle. you can select the desired time between checks by adjusting a built-in clock divider. software interface in the quartus ii software version 4.1 and later, you can turn on the automated error detection crc feature in the device & pin options dialog box. this dialog box allows you to enable the feature and set the internal frequency of the crc between 400 khz to 100 mhz. this controls the rate that the crc circuitr y verifies the internal configuration sram bits in the fpga device. for more information on crc, refer to an 357: error detection using crc in altera fpga devices . temperature- sensing diode stratix gx devices include a diode-connected transistor for use as a temperature sensor in power manageme nt. this diode is used with an external digital thermometer devi ce such as a max1617a or max1619 from maxim integrated products. these devices steer bias current through the stratix gx diode, measuring forward voltage and converting this reading to temperature in the form of an 8-bit signed number (7 bits plus sign). the external device?s output represents the package temperature of the stratix gx device and can be used for intelligent power management. the diode requires two pins ( tempdiodep and tempdioden ) on the stratix gx device to connect to the external temperature-sensing device, as shown in figure 5?4 . the temperature-sensing diode is a passive element and therefore can be used before the stratix gx device is powered.
altera corporation 5?9 february 2005 stratix gx device handbook, volume 1 configuration & testing figure 5?4. external temperature-sensing diode table 5?2 shows the specifications for bias voltage and current of the stratix gx temperature-sensing diode. the temperature-sensing diode works for the entire operating range shown in figure 5?5 . table 5?2. temperature-sensing di ode electrical characteristics parameter minimum typical maximum units i bias high 80 100 120 a i bias low 8 10 12 a v bp ? v bn 0.3 0.9 v v bn 0.7 v series resistance 3 w stratix gx device temperature-sensin g device tempdiodep tempdioden
5?10 altera corporation stratix gx device handbook, volume 1 february 2005 temperature-sensing diode figure 5?5. temperature versus te mperature-sensing diode voltage 0.90 0.85 0.95 0.75 0.65 voltage (across diode) temperature ( c) 0.55 0.45 0.60 0.50 0.40 0.70 0.80 ? 55 ? 30 ? 520457095120 10 a bias current 100 a bias current
altera corporation 6?1 june 2006 6. dc & switching characteristics operating conditions stratix ? gx devices are offered in both co mmercial and industrial grades. however, industrial-grade devices may have limited speed-grade availability. tables 6?1 through 6?12 provide information on absolute maximum ratings, recommended operating cond itions, dc operating conditions, and transceiver block absolute maximum ratings. notes for tables 6?1 through 6?6 immediately follow table 6?6 , notes for table 6?7 immediately follow that table, and notes for tables 6?8 through 6?12 immediately follow table 6?12 . table 6?1. stratix gx device absolute maximum ratings notes (1) , (2) symbol parameter conditi ons minimum maximum unit v ccint supply voltage with respect to ground (3) ?0.5 2.4 v v ccio ?0.5 4.6 v v i dc input voltage ?0.5 4.6 v i out dc output current, per pin ?25 25 ma t stg storage temperature no bias ?65 150 c t amb ambient temperature under bias ?65 135 c t j junction temperature bga packages under bias 135 c table 6?2. stratix gx device recommended operating conditions (part 1 of 2) note (7) , (12) , (13) symbol parameter conditions minimum maximum unit v ccint supply voltage for internal logic and input buffers (4) 1.425 1.575 v v ccio supply voltage for output buffers, 3.3-v operation (4) , (5) 3.00 (3.135) 3.60 (3.465) v supply voltage for output buffers, 2.5-v operation (4) 2.375 2.625 v supply voltage for output buffers, 1.8-v operation (4) 1.71 1.89 v supply voltage for output buffers, 1.5-v operation (4) 1.4 1.6 v v i input voltage (3) , (6) ?0.5 4.1 v sgx51006-1.2
6?2 altera corporation stratix gx device handbook, volume 1 june 2006 operating conditions v o output voltage 0 v ccio v t j operating junction temperature for commercial use 085 c for industrial use ?40 100 c table 6?3. stratix gx device dc operating conditions note (12) symbol parameter conditions minimum typical maximum unit i i input pin leakage current v i = v cciomax to 0 v (8) ?10 10 a i oz tri-stated i/o pin leakage current v o = v cciomax to 0 v (8) ?10 10 a r conf value of i/o pin pull- up resistor before and during configuration v ccio = 3.0 v (9) 20 50 k v ccio = 2.375 v (9) 30 80 k v ccio = 1.71 v (9) 60 150 k table 6?4. stratix gx transceiver block absolute maximum ratings symbol parameter conditions minimum maximum units v cca transceiver block supply voltage commercial and industrial ?0.5 4.6 v v ccp transceiver block supply voltage commercial and industrial ?0.5 2.4 v v ccr transceiver block supply voltage commercial and industrial ?0.5 2.4 v v cct transceiver block supply voltage commercial and industrial ?0.5 2.4 v v ccg transceiver block supply voltage commercial and industrial ?0.5 2.4 v receiver input voltage v icm v id single / 2 commercial and industrial 1.675 (10) , (13) v refclkb input voltage v icm v id single / 2 commercial and industrial 1.675 (10) , (13) v table 6?2. stratix gx device recommended operating conditions (part 2 of 2) note (7) , (12) , (13) symbol parameter conditions minimum maximum unit
altera corporation 6?3 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics table 6?5. stratix gx transceiver block operating conditions symbol parameter conditions minimum typical maximum units v cca transceiver block supply voltage commercial and industrial 3.135 3.3 3.465 v v ccp transceiver block supply voltage commercial and industrial 1.425 1.5 1.575 v v ccr transceiver block supply voltage commercial and industrial 1.425 1.5 1.575 v v cct transceiver block supply voltage commercial and industrial 1.425 1.5 1.575 v v ccg transceiver block supply voltage commercial and industrial 1.425 1.5 1.575 v v id (differential p-p) receiver input differential voltage swing commercial and industrial 170 2,000 mv refclkb input differential voltage swing commercial and industrial 400 2,000 mv v icm receiver input common mode voltage commercial and industrial 1,025 1,100 1,175 mv v od (differential p-p) transmitter output differential voltage commercial and industrial 350 1,600 mv v ocm transmitter output common mode voltage commercial and industrial 750 mv r ref (11) reference resistor commercial and industrial 2k ?1% 2k 2k +1% table 6?6. stratix gx transceiver bloc k on-chip termination (part 1 of 2) symbol parameter conditions min typ max units rx receiver termination commercial and industrial, 100- setting 103 108 113 commercial and industrial, 120- setting 120 128 134 commercial and industrial, 150- setting 149 158 167 tx transmitter termination commercial and industrial, 100- setting 103 108 113 commercial and industrial, 120- setting 120 128 134 commercial and industrial, 150- setting 149 158 167
6?4 altera corporation stratix gx device handbook, volume 1 june 2006 operating conditions refclkb dedicated transceiver clock termination commercial and industrial, 100- setting 103 108 113 commercial and industrial, 120- setting 120 128 134 commercial and industrial, 150- setting 149 158 167 notes to ta b l e s 6 ? 1 through 6?6 : (1) see the operating requirements for altera devices data sheet . (2) conditions beyond those listed in table 6?1 may cause permanent damage to a device. additionally, device operation at the absolute maximum ratings for extended pe riods of time may have adve rse affects on the device. (3) minimum dc input is ?0.5 v. during transitions, the in puts may undershoot to ?2.0 v or overshoot to 4.6 v for input currents less than 100 ma and pe riods shorter than 20 ns. (the information in this note do es not include the transceiver pins. see note 13 for information about the transien t voltage on the transceiver pins.) (4) maximum v cc rise time is 100 ms, and v cc must rise monotonically. (5) v ccio maximum and minimum conditions for lvpecl, lvds, and 3.3-v pcml are shown in parentheses. (6) all pins, including dedicated inputs, clock, i/o, and jtag pins, may be driven before v ccint and v ccio are powered. (7) typical values are for t a = 25 c, v ccint = 1.5 v, and v ccio = 1.5 v, 1.8 v, 2.5 v, and 3.3 v. (8) this value is specified for normal device operation. the value may vary during power-up. this applies for all v ccio settings (3.3, 2.5, 1.8, and 1.5 v). (9) pin pull-up resistance values decrease if an external source drives the pin higher than v ccio . (10) the device can tolerate prolonged op eration at this absolute maximum, as long as the maximum specification is not violated. (11) each usable quad requires its own r ref resistor path to ground. for example, the ?d? in the ep1sgx25dc1020 device code means it has two us able quad so two different r ref pins must be connected to a r ref resistor each to ground. the dc signal on the r ref pin must be as clean as possible. ensure that no noise is coupled to this pin. (12) the stratix gx device?s recommended operating con ditions do not include the transceiver. refer to tables 6?4 to 6?7 . (13) minimum dc input to the transceiver pins is ?0.5 v. du ring transitions, the transcei ver pins may undershoot to ?0.5 v or overshoot to 3.5 v for input currents less than 100 ma and periods shorter than 20 ns. table 6?7. stratix gx transceiver bl ock ac specification (part 1 of 7) symbol / description conditions -5 commercial speed grade (1) -6 commercial & industrial speed grade (1) -7 commercial & industrial speed grade (1) unit min typ max min typ max min typ max power per quadrant (pcs + pma) 3.125 gbps, 400- mv v od 0 pre-emphasis 450 450 mw table 6?6. stratix gx transceiver bloc k on-chip termination (part 2 of 2) symbol parameter conditions min typ max units
altera corporation 6?5 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics reference clock jitter tolerance (peak-to- peak) jitter components <20 mhz 20 20 20 ps wideband 50 50 50 ps reference input clock frequency dedicated refclkb pins 25 650 25 650 25 312.5 mhz pld clock resources 25 325 25 325 25 156.25 mhz receiver serial data rate (general) commercial / industrial 614 3,187.5 614 3,187.5 614 2,500 mbps serial data rate (8b/10b encoded) commercial / industrial 500 3,187.5 500 3,187.5 500 2,500 mbps parallel transceiver/ logic array interface speed 20 398.4 20 375 20 312.5 mhz rate matching frequency tolerance xaui mode only 100 100 100 ppm 8b/10b custom receiver jitter tolerance using encoded cjpat note (2) deterministic jitter 500 mbps 0.45 0.45 0.45 ui total jitter 500 mbps 0.71 0.71 0.71 ui fibre channel receiver jitter tole rance using 8b/10b encoded cjtpat note (2) deterministic jitter 1.0625 gbps 0.37 0.37 0.37 ui total jitter 1.0625 gbps 0.68 0.68 0.68 ui table 6?7. stratix gx transceiver bl ock ac specification (part 2 of 7) symbol / description conditions -5 commercial speed grade (1) -6 commercial & industrial speed grade (1) -7 commercial & industrial speed grade (1) unit min typ max min typ max min typ max
6?6 altera corporation stratix gx device handbook, volume 1 june 2006 operating conditions sinusoidal jitter f = 42.5 khz at 1.0625 gbps 1.5 1.5 1.5 ui f = 637 khz at 1.0625 gbps 0.1 0.1 0.1 ui deterministic jitter 2.125 gbps 0.33 0.33 0.33 ui total jitter 2.125 gbps 0.62 0.62 0.62 ui sinusoidal jitter f = 85 khz at 2.125 gbps 1.5 1.5 1.5 ui f = 1,274 khz at 2.125 gbps 0.1 0.1 0.1 ui serial rapid i/o receiver jitter to lerance using 8b/10b encoded cjpat note (2) deterministic jitter 1.25 gbps 0.45 0.45 0.45 ui total jitter 1.25 gbps 0.71 0.71 0.71 ui deterministic jitter 2.5 gbps 0.41 0.41 0.41 ui total jitter 2.5 gbps 0.65 0.65 0.65 ui deterministic jitter 3.125 gbps 0.36 0.36 n/a ui total jitter 3.125 gbps 0.60 0.60 n/a ui sonet receiver jitter tolerance using prbs23 note (2) sinusoidal jitter f = 6 khz at 2.48832 gbps 1.5 1.5 1.5 ui f = 1 mhz at 2.48832 gbps 0.15 0.15 0.15 ui xaui receiver jitter toleranc e using 8b/10b encoded cjpat note (2) deterministic jitter 3.125 gbps 0.37 0.37 n/a ui total jitter 3.125 gbps 0.65 0.65 n/a ui table 6?7. stratix gx transceiver bl ock ac specification (part 3 of 7) symbol / description conditions -5 commercial speed grade (1) -6 commercial & industrial speed grade (1) -7 commercial & industrial speed grade (1) unit min typ max min typ max min typ max
altera corporation 6?7 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics sinusoidal jitter f = 22.1 khz at 3.125 gbps 8.5 8.5 n/a f = 1.875 mhz at 3.125 gbps 0.1 0.1 n/a f = 20 mhz at 3.125 gbps 0.1 0.1 n/a ber (12) 10 -12 10 -12 10 -12 receive latency (4) single width 7 32 7 32 7 32 (3) double width 5 19 5 19 5 19 (3) channel to channel bit skew tolerance (5) , (6) xaui mode / inter-quadrant only 40 40 n/a ui (7) run-length (8) 80 80 80 ui receive return loss (differential) 100 mhz to 2.5 ghz ?10 ?10 ?10 db receive return loss (common mode) 100 mhz to 2.5 ghz ?6 ?6 ?6 db transmitter serial data rate commercial / industrial 500 3,187.5 500 3,187.5 500 2,500 mbps parallel transceiver/ core interface speed 20 398.4 20 375 20 312.5 mhz 8b/10b custom transmitte r jitter using encoded crpat note (9) deterministic jitter 500 mbps pre-emphasis = 1 v od = 1,400 mv 0.11 0.11 0.11 ui total jitter 0.18 0.18 0.18 ui table 6?7. stratix gx transceiver bl ock ac specification (part 4 of 7) symbol / description conditions -5 commercial speed grade (1) -6 commercial & industrial speed grade (1) -7 commercial & industrial speed grade (1) unit min typ max min typ max min typ max
6?8 altera corporation stratix gx device handbook, volume 1 june 2006 operating conditions fibre channel transmit ter jitter using 8b/10b encoded crpat note (9) deterministic jitter 1.0625 gbps pre-emphasis = 0 v od = 1,200 mv 0.09 0.09 0.09 ui total jitter 0.17 0.17 0.17 ui deterministic jitter 2.125 gbps pre-emphasis= 1 v od = 1,200 mv 0.16 0.16 0.16 ui total jitter 0.33 0.33 0.33 ui serial rapid i/o short run transmitt er jitter using 8b/10b encoded crpat note (9) deterministic jitter 1.25 gbps pre-emphasis = 1 v od = 1,600 mv 0.09 0.09 0.09 ui total jitter 0.17 0.17 0.17 ui deterministic jitter 2.5 gbps pre-emphasis = 1 v od = 800 mv 0.15 0.15 0.15 ui total jitter 0.32 0.32 0.32 ui deterministic jitter 3.125 gbps pre-emphasis = 1 v od = 800 mv 0.15 0.15 n/a ui total jitter 0.32 0.32 n/a ui serial rapid i/o long run transmitter jitter using 8b/10b encoded crpat note (9) deterministic jitter 1.25 gbps pre-emphasis = 1 v od = 1,600 mv 0.09 0.09 0.09 ui total jitter 0.17 0.17 0.17 ui deterministic jitter 2.5 gbps pre-emphasis = 2 v od = 1,400 mv 0.18 0.18 0.18 ui total jitter 0.35 0.35 0.35 ui deterministic jitter 3.125 gbps pre-emphasis = 2 v od = 1,400 mv 0.20 0.20 n/a ui total jitter 0.37 0.37 n/a ui sonet transmitter jitter prbs23 note (9) total jitter 2.48832 gbps pre-emphasis = 1 v od = 800 mv 0.20 0.20 0.20 ui table 6?7. stratix gx transceiver bl ock ac specification (part 5 of 7) symbol / description conditions -5 commercial speed grade (1) -6 commercial & industrial speed grade (1) -7 commercial & industrial speed grade (1) unit min typ max min typ max min typ max
altera corporation 6?9 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics xaui transmitter jitter using 8b/10b encoded cjpat note (9) deterministic jitter 3.125 gbps pre-emphasis = 0 v od = 1,200 mv 0.15 0.15 n/a ui total jitter 0.32 0.32 n/a ui jitter transfer bandwidth (10) low bandwidth setting at 3.125 gbps 3 3 n/a mhz high bandwidth setting at 3.125 gbps 4.7 4.7 n/a mhz low bandwidth setting at 2.5 gbps 3.2 3.2 3.2 mhz high bandwidth setting at 2.5 gbps 4.3 4.3 4.3 mhz output t rise 20% to 80% 60 130 60 130 60 130 ps output t fall 80% to 20% 60 130 60 130 60 130 ps transmit latency (11) single width 3 8 3 8 3 8 (3) double width 3 7 3 7 3 7 (3) intra differential pair skew 10 10 10 ps channel to channel skew within a single quadrant 50 50 50 ps table 6?7. stratix gx transceiver bl ock ac specification (part 6 of 7) symbol / description conditions -5 commercial speed grade (1) -6 commercial & industrial speed grade (1) -7 commercial & industrial speed grade (1) unit min typ max min typ max min typ max
6?10 altera corporation stratix gx device handbook, volume 1 june 2006 operating conditions output return loss 100 mhz to 2.5 ghz ?10 ?10 ?10 db notes to ta b l e 6 ? 7 : (1) all numbers for the -6 and -7 speed grades are for bo th commercial and industrial unless specified otherwise in the conditions column. speed grade -5 is avai lable only for commercial specifications. (2) not all v id and equalizer values will get the same results. the condition for the specification was that the v id before jitter was added is 1,000 mv and the equalizer was set to the maximum condit ion of 111 (equalizer control setting = 4 in the megawizard plug-in manager). (3) number of parallel clocks. (4) receive latency delay from serial rece iver indata to parallel receiver data. (5) per ieee standard 802.3ae @ 3.125 for ?5 and ?6. (6) the specification is for channel aligner tolerance. (7) ui = unit interval. (8) run-length conditions are true for a ll data rates, but the average transition density must be enough to keep the receiver phase aligned and the overall data must be dc balanced. (9) not all combinations of v od and pre-emphasis will get the same results. (10) the numbers are for 3.125-gbps data rate fo r ?5 and ?6 devices and 2.5 gbps for ?7 devices. (11) transmitter latency delay from parallel transceiver data to serial transceiver out data. (12) the receiver operates with a ber of better than 10 -12 in the presence of an input sign al as defined in the xaui driver template for 3.125 gbps and in the pci exp transmitter eye mask for 2.5 gbps. table 6?8. lvttl specifications symbol parameter conditi ons minimum maximum units v ccio output supply voltage 3.0 3.6 v v ih high-level input voltage 1.7 4.1 v v il low-level input voltage ?0.5 0.7 v v oh high-level output voltage i oh = ?4 to ?24 ma (1) 2.4 v v ol low-level output voltage i ol = 4 to 24 ma (1) 0.45 v table 6?9. lvcmos specifications symbol parameter conditi ons minimum maximum units v ccio output supply voltage 3.0 3.6 v v ih high-level input voltage 1.7 4.1 v v il low-level input voltage ?0.5 0.7 v table 6?7. stratix gx transceiver bl ock ac specification (part 7 of 7) symbol / description conditions -5 commercial speed grade (1) -6 commercial & industrial speed grade (1) -7 commercial & industrial speed grade (1) unit min typ max min typ max min typ max
altera corporation 6?11 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics v oh high-level output voltage v ccio = 3.0, i oh = ?0.1 ma v ccio ? 0.2 v v ol low-level output voltage v ccio = 3.0, i ol = 0.1 ma 0.2 v table 6?10. 2.5-v i/o specifications note (1) symbol parameter conditi ons minimum maximum units v ccio output supply voltage 2.375 2.625 v v ih high-level input voltage 1.7 4.1 v v il low-level input voltage ?0.5 0.7 v v oh high-level output voltage i oh = ?0.1 ma 2.1 v i oh = ?1 ma 2.0 v i oh = ?2 to ?16 ma (1) 1.7 v v ol low-level output voltage i ol = 0.1 ma 0.2 v i oh = 1 ma 0.4 v i oh = 2 to 16 ma (1) 0.7 v table 6?11. 1.8-v i/o specifications symbol parameter conditi ons minimum maximum units v ccio output supply voltage 1.65 1.95 v v ih high-level input voltage 0.65 v ccio 2.25 v v il low-level input voltage ?0.3 0.35 v ccio v v oh high-level output voltage i oh = ?2 to ?8 ma (1) v ccio ? 0.45 v v ol low-level output voltage i ol = 2 to 8 ma (1) 0.45 v table 6?12. 1.5-v i/o specifications (part 1 of 2) symbol parameter conditi ons minimum maximum units v ccio output supply voltage 1.4 1.6 v v ih high-level input voltage 0.65 v ccio v ccio + 0.3 v v il low-level input voltage ?0.3 0.35 v ccio v v oh high-level output voltage i oh = ?2 ma (1) 0.75 v ccio v table 6?9. lvcmos specifications symbol parameter conditi ons minimum maximum units
6?12 altera corporation stratix gx device handbook, volume 1 june 2006 operating conditions figures 6?1 through 6?3 show receiver input and transmitter output waveforms, respectively, for all differential i/o standards (lvds, 3.3-v pcml, lvpecl, and hypert ransport technology). figure 6?1. receiver input waveform s for differential i/o standards v ol low-level output voltage i ol = 2 ma (1) 0.25 v ccio v note to ta b l e s 6 ? 8 through 6?12 : (1) drive strength is programmable ac cording to values in found in the stratix gx architecture chapter of the stratix gx device handbook, volume 1 . table 6?12. 1.5-v i/o specifications (part 2 of 2) symbol parameter conditi ons minimum maximum units single-ended waveform differential waveform (v id (differential) = 2 x v id (single-ended)) positive channel (p) = v oh negative channel (n) = v ol ground v id v id v id p ? n = 0 v v cm
altera corporation 6?13 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics figure 6?2. receiver input wave form example with values notes to figure 6?2 : (1) the values in this figure are for example only. (2) these values must meet the vo ltages specified in the section ?operating conditions? on page 6?1 . (3) if internal termination is used, the co mmon mode is generated after the pins. figure 6?3. transmitter output wavefo rms for differential i/o standards single-ended waveform: what is applied to the pin ( 2 ) differential waveform: as seen by the buffer or by subtra c tion on an os c illos c ope positive channel (p) negative channel (n) ground v id = 1 v v icm = 1.175 v ( 3 ) p - n = 0 v v id = 1 v d i ffere n t i a l v i d = 2 * v i d ( s in g l e -en ded ) = 2 v v id = 1 v v ih = 1.175 v + 0.5 v = 1.675 v v il = 1.175 v - 0.5 v = 0.675 v single-ended waveform differential waveform (v id (differential) = 2 x v id (single-ended)) positive channel (p) = v oh negative channel (n) = v ol ground v id v id v id p ? n = 0 v v cm
6?14 altera corporation stratix gx device handbook, volume 1 june 2006 operating conditions tables 6?13 through 6?33 provide information about specifications and bus hold parameters for 1.5-v stratix gx devices. notes for tables 6?14 through 6?33 immediately follow table 6?33 . table 6?13. 3.3-v lvds i/o specifications symbol parameter conditions minimum typical maximum units v ccio i/o supply voltage 3.135 3.3 3.465 v v id (1) input differential voltage swing (single-ended) 0.1 v < v cm < 1.1 v w = 1 through 10 300 1,000 mv 1.1 v < v cm < 1.6 v w = 1 200 1,000 mv 1.1 v < v cm < 1.6 v w = 2 through 10 100 1,000 mv 1.6 v < v cm < 1.8 v w = 1 through 10 300 1,000 mv v icm (1) input common-mode voltage lv d s 0.3 v < v id < 1.0 v w = 1 through 10 100 1,100 mv lv d s 0.3 v < v id < 1.0 v w = 1 through 10 1,600 1,800 mv lv d s 0.2 v < v id < 1.0 v w = 1 1,100 1,600 mv lv d s 0.1 v < v id < 1.0 v w = 2 through 10 1,100 1,600 mv v od differential output voltage (single ended) r l = 100 250 375 550 mv v od change in v od between high and low r l = 100 50 mv v ocm output common-mode voltage r l = 100 1,125 1,200 1,375 mv v ocm change in v ocm between high and low r l = 100 50 mv r l receiver differential input resistor, external 90 100 110 note to table 6?13 : (1) for up to 1 gbps in dpa mode and 840 mbps in non-dpa mode
altera corporation 6?15 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics table 6?14. 3.3-v pcml specifications symbol parameter conditions minimum typical maximum units v ccio i/o supply voltage 3.135 3.3 3.465 v v id input differential voltage swing (single-ended) 300 600 mv v icm input common mode voltage 1.5 3.465 v v od output differential voltage (single-ended) 300 370 500 mv v od change in v od between high and low 50 mv v ocm output common mode voltage 2.5 2.85 3.3 v v ocm change in v ocm between high and low 50 mv v t output termination voltage v ccio v r 1 output external pull-up resistors 45 50 55 r 2 output external pull-up resistors 45 50 55 table 6?15. lvpecl specifications symbol parameter conditions minimum typical maximum units v ccio i/o supply voltage 3.135 3.3 3.465 v v id input differential voltage swing (single-ended) 300 1,000 mv v icm input common mode voltage 12v v od differential output voltage (single ended) r l = 100 525 700 970 mv v ocm output common mode voltage r l = 100 1.5 1.7 1.9 v r l receiver differential input resistor, external 90 100 110
6?16 altera corporation stratix gx device handbook, volume 1 june 2006 operating conditions table 6?16. hypertransport specifications symbol parameter conditions minimum typical maximum units v ccio i/o supply voltage 2.375 2.5 2.625 v v od differential output voltage (single ended) r l = 100 380 485 820 mv v od change in between high and low r l = 100 50 mv v ocm output common mode voltage r l = 100 440 650 780 mv v ocm change in between high and low r l = 100 50 mv v id differential input voltage swing (single-ended) 300 900 mv v icm input common mode voltage 300 900 mv r l receiver differential input resistor, external 90 100 110 table 6?17. 3.3-v pci specifications symbol parameter conditions minimum typical maximum units v ccio output supply voltage 3.0 3.3 3.6 v v ih high-level input voltage 0.5 v ccio v ccio + 0.5 v v il low-level input voltage ?0.5 0.3 v ccio v v oh high-level output voltage i out = ?500 a0.9 v ccio v v ol low-level output voltage i out = 1,500 a0.1 v ccio v table 6?18. pci-x specifications (part 1 of 2) symbol parameter conditions minimum typical maximum units v ccio output supply voltage 3.0 3.6 v v ih high-level input voltage 0.5 v ccio v ccio + 0.5 v v il low-level input voltage ?0.5 0.35 v ccio v
altera corporation 6?17 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics v ipu input pull-up voltage 0.7 v ccio v v oh high-level output voltage i out = ?500 a0.9 v ccio v v ol low-level output voltage i out = 1,500 a0.1 v ccio v table 6?19. gtl+ i/o specifications symbol parameter conditions minimum typical maximum units v tt termination voltage 1.35 1.5 1.65 v v ref reference voltage 0.88 1.0 1.12 v v ih high-level input voltage v ref + 0.1 v v il low-level input voltage v ref ? 0.1 v v ol low-level output voltage i ol = 36 ma (1) 0.65 v table 6?20. gtl i/o specifications symbol parameter conditions minimum typical maximum units v tt termination voltage 1.14 1.2 1.26 v v ref reference voltage 0.74 0.8 0.86 v v ih high-level input voltage v ref + 0.05 v v il low-level input voltage v ref ? 0.05 v v ol low-level output voltage i ol = 40 ma (1) 0.4 v table 6?21. sstl-18 class i s pecifications (part 1 of 2) symbol parameter conditions minimum typical maximum units v ccio output supply voltage 1.65 1.8 1.95 v v ref reference voltage 0.8 0.9 1.0 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ih(dc) high-level dc input voltage v ref + 0.125 v table 6?18. pci-x specifications (part 2 of 2) symbol parameter conditions minimum typical maximum units
6?18 altera corporation stratix gx device handbook, volume 1 june 2006 operating conditions v il(dc) low-level dc input voltage v ref ? 0.125 v v ih(ac) high-level ac input voltage v ref + 0.275 v v il(ac) low-level ac input voltage v ref ? 0.275 v v oh high-level output voltage i oh = ?6.7 ma (1) v tt + 0.475 v v ol low-level output voltage i ol = 6.7 ma (1) v tt ? 0.475 v table 6?22. sstl-18 clas s ii specifications symbol parameter conditions minimum typical maximum units v ccio output supply voltage 1.65 1.8 1.95 v v ref reference voltage 0.8 0.9 1.0 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ih(dc) high-level dc input voltage v ref + 0.125 v v il(dc) low-level dc input voltage v ref ? 0.125 v v ih(ac) high-level ac input voltage v ref + 0.275 v v il(ac) low-level ac input voltage v ref ? 0.275 v v oh high-level output voltage i oh = ?13.4 ma (1) v tt + 0.630 v v ol low-level output voltage i ol = 13.4 ma (1) v tt ? 0.630 v table 6?23. sstl-2 class i specifications (part 1 of 2) symbol parameter conditions minimum typical maximum units v ccio output supply voltage 2.375 2.5 2.625 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ref reference voltage 1.15 1.25 1.35 v v ih high-level input voltage v ref + 0.18 3.0 v v il low-level input voltage ?0.3 v ref ? 0.18 v table 6?21. sstl-18 class i s pecifications (part 2 of 2) symbol parameter conditions minimum typical maximum units
altera corporation 6?19 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics v oh high-level output voltage i oh = ?8.1 ma (1) v tt + 0.57 v v ol low-level output voltage i ol = 8.1 ma (1) v tt ? 0.57 v table 6?24. sstl-2 class ii specifications symbol parameter conditions minimum typical maximum units v ccio output supply voltage 2.3 2.5 2.7 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ref reference voltage 1.15 1.25 1.35 v v ih high-level input voltage v ref + 0.18 v ccio + 0.3 v v il low-level input voltage ?0.3 v ref ? 0.18 v v oh high-level output voltage i oh = ?16.4 ma (1) v tt + 0.76 v v ol low-level output voltage i ol = 16.4 ma (1) v tt ? 0.76 v table 6?25. sstl-3 class i specifications symbol parameter conditions minimum typical maximum units v ccio output supply voltage 3.0 3.3 3.6 v v tt termination voltage v ref ? 0.05 v ref v ref + 0.05 v v ref reference voltage 1.3 1.5 1.7 v v ih high-level input voltage v ref + 0.2 v ccio + 0.3 v v il low-level input voltage ?0.3 v ref ? 0.2 v v oh high-level output voltage i oh = ?8 ma (1) v tt + 0.6 v v ol low-level output voltage i ol = 8 ma (1) v tt ? 0.6 v table 6?26. sstl-3 class ii specifications (part 1 of 2) symbol parameter conditions minimum typical maximum units v ccio output supply voltage 3.0 3.3 3.6 v v tt termination voltage v ref ? 0.05 v ref v ref + 0.05 v v ref reference voltage 1.3 1.5 1.7 v v ih high-level input voltage v ref + 0.2 v ccio + 0.3 v table 6?23. sstl-2 class i specifications (part 2 of 2) symbol parameter conditions minimum typical maximum units
6?20 altera corporation stratix gx device handbook, volume 1 june 2006 operating conditions v il low-level input voltage ?0.3 v ref ? 0.2 v v oh high-level output voltage i oh = ?16 ma (1) v tt + 0.8 v v ol low-level output voltage i ol = 16 ma (1) v tt ? 0.8 v table 6?27. 3.3-v agp 2 specifications symbol parameter conditions minimum typical maximum units v ccio output supply voltage 3.15 3.3 3.45 v v ref reference voltage 0.39 v ccio 0.41 v ccio v v ih high-level input voltage (2) 0.5 v ccio v ccio + 0.5 v v il low-level input voltage (2) 0.3 v ccio v v oh high-level output voltage i out = ?0.5 ma 0.9 v ccio 3.6 v v ol low-level output voltage i out = 1.5 ma 0.1 v ccio v table 6?28. 3.3-v agp 1 specifications symbol parameter conditions minimum typical maximum units v ccio output supply voltage 3.15 3.3 3.45 v v ih high-level input voltage (2) 0.5 v ccio v ccio + 0.5 v v il low-level input voltage (2) 0.3 v ccio v v oh high-level output voltage i out = ?0.5 ma 0.9 v ccio 3.6 v v ol low-level output voltage i out = 1.5 ma 0.1 v ccio v table 6?29. 1.5-v hstl class i specifications (part 1 of 2) symbol parameter conditions minimum typical maximum units v ccio output supply voltage 1.4 1.5 1.6 v v ref input reference voltage 0.68 0.75 0.9 v v tt termination voltage 0.7 0.75 0.8 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v table 6?26. sstl-3 class ii specifications (part 2 of 2) symbol parameter conditions minimum typical maximum units
altera corporation 6?21 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics v oh high-level output voltage i oh = 8 ma (1) v ccio ? 0.4 v v ol low-level output voltage i oh = ?8 ma (1) 0.4 v table 6?30. 1.5-v hstl class ii specifications symbol parameter conditions minimum typical maximum units v ccio output supply voltage 1.4 1.5 1.6 v v ref input reference voltage 0.68 0.75 0.9 v v tt termination voltage 0.7 0.75 0.8 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = 16 ma (1) v ccio ? 0.4 v v ol low-level output voltage i oh = ?16 ma (1) 0.4 v table 6?31. 1.5-v differential hstl specifications symbol parameter conditions minimum typical maximum units v ccio i/o supply voltage 1.4 1.5 1.6 v v dif (dc) dc input differential voltage 0.2 v v cm (dc) dc common mode input voltage 0.68 0.9 v v dif (ac) ac differential input voltage 0.4 v table 6?32. ctt i/o specifications (part 1 of 2) symbol parameter conditions minimum typical maximum units v ccio output supply voltage 3.0 3.3 3.6 v v tt /v ref termination and input reference voltage 1.35 1.5 1.65 v v ih high-level input voltage v ref + 0.2 v v il low-level input voltage v ref ? 0.2 v table 6?29. 1.5-v hstl class i specifications (part 2 of 2) symbol parameter conditions minimum typical maximum units
6?22 altera corporation stratix gx device handbook, volume 1 june 2006 power consumption power consumption detailed power consumption informat ion for stratix gx devices will be released when available. timing model the directdrive ? technology and multitrack ? interconnect ensure predictable performance, accurate simulation, and ac curate timing analysis across al l stratix gx device densities and speed grades. this section describes and specifies the pe rformance, internal, external, and pll timing specifications. all specifications are representative of worst-case supply voltage and junction temperature conditions. v oh high-level output voltage i oh = ?8 ma v ref + 0.4 v v ol low-level output voltage i ol = 8 ma v ref ? 0.4 v i o output leakage current (when output is high z ) gnd v out v ccio ?10 10 a table 6?33. bus hold parameters parameter conditions v ccio level units 1.5 v1.8 v2.5 v3.3 v min max min max min max min max low sustaining current v in > v il (maximum) 25 30 50 70 a high sustaining current v in < v ih (minimum) ?25 ?30 ?50 ?70 a low overdrive current 0 v < v in < v ccio 160 200 300 500 a high overdrive current 0 v < v in < v ccio ?160 ?200 ?300 ?500 a bus-hold trip point 0.5 1.0 0.68 1.07 0.7 1.7 0.8 2.0 v notes to tables 6?14 through 6?33 : (1) drive strength is programmable according to values in the stratix gx architecture chapter of the stratix gx device handbook, volume 1 . (2) v ref specifies the center point of the switching range. table 6?32. ctt i/o specifications (part 2 of 2) symbol parameter conditions minimum typical maximum units
altera corporation 6?23 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics preliminary & final timing timing models can have either preliminary or final status. the quartus ? ii software displays an informational message during the design compilation if the timing models are preliminary. table 6?34 shows the status of the stra tix gx device timing models. preliminary status means the timing model is subject to change. initially, timing numbers are created using simulation results, process data, and other known parameters. these tests are used to make the preliminary numbers as close to the actual timing parameters as possible. final timing numbers are based on ac tual device operation and testing. these numbers reflect the actual performance of the device under worst-case voltage and juncti on temperature conditions. performance table 6?35 shows stratix gx device performance for some common designs. all performance values were obtained with quartus ii software compilation of lpm, or megacore ? functions for the fir and fft designs. table 6?34. stratix gx device timing model status device preliminary final ep1sgx10 ? v ep1sgx25 ? v ep1sgx40 ? v table 6?35. stratix gx device performance (part 1 of 3) notes (1) , (2) applications resources used performance les trimatrix memory blocks dsp blocks -5 speed grade -6 speed grade -7 speed grade units le 16-to-1 multiplexer (1) 22 0 0 407.83 324.56 288.68 mhz 32-to-1 multiplexer (3) 46 0 0 318.26 255.29 242.89 mhz 16-bit counter 16 0 0 422.11 422.11 390.01 mhz 64-bit counter 64 0 0 321.85 290.52 261.23 mhz
6?24 altera corporation stratix gx device handbook, volume 1 june 2006 timing model tr i m a t r i x memory m512 block simple dual-port ram 32 18 bit 0 1 0 317.76 277.62 241.48 mhz fifo 32 18 bit 30 1 0 319.18 278.86 242.54 mhz tr i m a t r i x memory m4k block simple dual-port ram 128 36 bit 0 1 0 290.86 255.55 222.27 mhz true dual-port ram 128 18 bit 0 1 0 290.86 255.55 222.27 mhz fifo 128 36 bit 34 1 0 290.86 255.55 222.27 mhz tr i m a t r i x memory m-ram block single port ram 4k 144 bit 1 1 0 255.95 223.06 194.06 mhz simple dual-port ram 4k 144 bit 0 1 0 255.95 233.06 194.06 mhz true dual-port ram 4k 144 bit 0 1 0 255.95 233.06 194.06 mhz single port ram 8k 72 bit 0 1 0 278.94 243.19 211.59 mhz simple dual-port ram 8k 72 bit 0 1 0 255.95 223.06 194.06 mhz true dual-port ram 8k 72 bit 0 1 0 255.95 223.06 194.06 mhz single port ram 16k 36 bit 0 1 0 280.66 254.32 221.28 mhz simple dual-port ram 16k 36 bit 0 1 0 269.83 237.69 206.82 mhz table 6?35. stratix gx device performance (part 2 of 3) notes (1) , (2) applications resources used performance les trimatrix memory blocks dsp blocks -5 speed grade -6 speed grade -7 speed grade units
altera corporation 6?25 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics tr i m a t r i x memory m-ram block true dual-port ram 16k 36 bit 0 1 0 269.83 237.69 206.82 mhz single port ram 32k 18 bit 0 1 0 275.86 244.55 212.76 mhz simple dual-port ram 32k 18 bit 0 1 0 275.86 244.55 212.76 mhz true dual-port ram 32k 18 bit 0 1 0 275.86 244.55 212.76 mhz single port ram 64k 9 bit 0 1 0 287.85 253.29 220.36 mhz simple dual-port ram 64k 9 bit 0 1 0 287.85 253.29 220.36 mhz true dual-port ram 64k 9 bit 0 1 0 287.85 253.29 220.36 mhz dsp block 9 9-bit multiplier (3) 0 0 1 335.0 293.94 255.68 mhz 18 18-bit multiplier (4) 0 0 1 278.78 237.41 206.52 mhz 36 36-bit multiplier (4) 0 0 1 148.25 134.71 117.16 mhz 36 36-bit multiplier (5) 0 0 1 278.78 237.41 206.52 mhz 18-bit, 4-tap fir filter 0 0 1 278.78 237.41 206.52 mhz larger designs 8-bit, 16-tap parallel fir filter 58 0 4 141.26 133.49 114.88 mhz 8-bit, 1,024-point fft function 870 5 1 261.09 235.51 205.21 mhz notes to table 6?35 : (1) these design performance numbers were obtained using the quartus ii software. (2) numbers not listed will be included in a future version of the data sheet. (3) this application uses regi stered inputs and outputs. (4) this application uses registered multiplier input and output stages within the dsp block. (5) this application uses registered multiplier input, pipeline, and output stages within the dsp block. table 6?35. stratix gx device performance (part 3 of 3) notes (1) , (2) applications resources used performance les trimatrix memory blocks dsp blocks -5 speed grade -6 speed grade -7 speed grade units
6?26 altera corporation stratix gx device handbook, volume 1 june 2006 timing model internal timing parameters internal timing parame ters are specified on a speed grade basis independent of device density. tables 6?36 through 6?42 describe the stratix gx device internal timing microparameters for les, ioes, trimatrix ? memory structures, dsp blocks, and multitrack interconnects. table 6?36. le internal timing microparameter descriptions symbol parameter t su le register setup time before clock t h le register hold time after clock t co le register clock-to-output delay t lut le combinational lut delay for data-in to data-out t clr minimum clear pulse width t pre minimum preset pulse width t clkhl minimum clock high or low time table 6?37. ioe internal timing microparameter descriptions symbol parameter t su ioe input and output register setup time before clock t h ioe input and output register hold time after clock t co ioe input and output regist er clock-to-output delay t pin2combout_r row input pin to ioe combinational output t pin2combout_c column input pin to ioe combinational output t combin2pin_r row ioe data input to combinational output pin t combin2pin_c column ioe data input to combinational output pin t clr minimum clear pulse width t pre minimum preset pulse width t clkhl minimum clock high or low time
altera corporation 6?27 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics table 6?38. dsp block internal timing microparameter descriptions symbol parameter t su input, pipeline, and output regist er setup time before clock t h input, pipeline, and output regi ster hold time after clock t co input, pipeline, and output regi ster clock-to-output delay t inreg2pipe9 input register to dsp bloc k pipeline register in 9 9-bit mode t inreg2pipe18 input register to dsp block pipeline register in 18 18-bit mode t pipe2outreg2add dsp block pipeline register to output register delay in two- multipliers adder mode t pipe2outreg4add dsp block pipeline register to output register delay in four- multipliers adder mode t pd9 combinational input to output delay for 9 9-bit mode t pd18 combinational input to output delay for 18 18-bit mode t pd36 combinational input to output delay for 36 36-bit mode t clr minimum clear pulse width t clkhl minimum clock high or low time table 6?39. m512 block internal t iming microparameter descriptions symbol parameter t m512rc synchronous read cycle time t m512wc synchronous write cycle time t m512weresu write or read enable setup time before clock t m512wereh write or read enable hold time after clock t m512datasu data setup time before clock t m512datah data hold time after clock t m512waddrsu write address setup time before clock t m512waddrh write address hold time after clock t m512raddrsu read address setup time before clock t m512raddrh read address hold time after clock t m512dataco1 clock-to-output delay when using output registers t m512dataco2 clock-to-output delay without output registers t m512clkhl minimum clock high or low time t m512clr minimum clear pulse width
6?28 altera corporation stratix gx device handbook, volume 1 june 2006 timing model table 6?40. m4k block internal timing microparameter descriptions symbol parameter t m4krc synchronous read cycle time t m4kwc synchronous write cycle time t m4kweresu write or read enable setup time before clock t m4kwereh write or read enable hold time after clock t m4kbesu byte enable setup time before clock t m4kbeh byte enable hold time after clock t m4kdataasu a port data setup time before clock t m4kdataah a port data hold time after clock t m4kaddrasu a port address setup time before clock t m4kaddrah a port address hold time after clock t m4kdatabsu b port data setup time before clock t m4kdatabh b port data hold time after clock t m4kaddrbsu b port address setup time before clock t m4kaddrbh b port address hold time after clock t m4kdataco1 clock-to-output delay when using output registers t m4kdataco2 clock-to-output delay without output registers t m4kclkhl minimum clock high or low time t m4kclr minimum clear pulse width table 6?41. m-ram block internal timing microparameter descriptions (part 1 of 2) symbol parameter t mramrc synchronous read cycle time t mramwc synchronous write cycle time t mramweresu write or read enable setup time before clock t mramwereh write or read enable hold time after clock t mrambesu byte enable setup time before clock t mrambeh byte enable hold time after clock t mramdataasu a port data setup time before clock t mramdataah a port data hold time after clock t mramaddrasu a port address setup time before clock t mramaddrah a port address hold time after clock
altera corporation 6?29 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics t mramdatabsu b port setup time before clock t mramdatabh b port hold time after clock t mramaddrbsu b port address setup time before clock t mramaddrbh b port address hold time after clock t mramdataco1 clock-to-output delay when using output registers t mramdataco2 clock-to-output delay without output registers t mramclkhl minimum clock high or low time t mramclr minimum clear pulse width table 6?42. routing delay internal timing microparameter descriptions symbol parameter t r4 delay for an r4 line with average loading; covers a distance of four lab columns t r8 delay for an r8 line with average loading; covers a distance of eight lab columns t r24 delay for an r24 line with average loading; covers a distance of 24 lab columns t c4 delay for an c4 line with average loading; covers a distance of four lab rows t c8 delay for an c8 line with average loading; covers a distance of eight lab rows t c16 delay for an c16 line with average loading; covers a distance of 16 lab rows t local local interconnect delay table 6?43. stratix gx reset & pll lock time parameter descriptions (part 1 of 2) symbol parameter t analogresetpw pulse width to power down analog circuits. t digitalresetpw pulse width to reset digital circuits t tx_pll_lock the time it takes the tx_pll to lock to the reference clock. table 6?41. m-ram block internal timing microparameter descriptions (part 2 of 2) symbol parameter
6?30 altera corporation stratix gx device handbook, volume 1 june 2006 timing model figure 6?4 shows the trimatrix memory waveforms for the m512, m4k, and m-ram timing parameters shown in tables 6?39 through 6?41 . figure 6?4. dual-port ram timi ng microparameter waveform t rx_freqlock the time until the clock recovery unit (cru) switches to data mode from lock to reference mode. t rx_freqlock2phaselock the time until cru phase locks to data after switching from lock to data mode. table 6?43. stratix gx reset & pll lock time parameter descriptions (part 2 of 2) symbol parameter wrclock wren wraddress data-in re g _data-out an-1 an a0 a1 a2 a3 a4 a5 din-1 din din4 din5 rdclock a6 din6 u nre g _data-out rden rdaddress bn b0 b1 b2 b3 doutn-2 doutn-1 doutn doutn-1 doutn dout0 t weresu t wereh t datac o 1 t datac o 2 t datasu t data h t wereh t weresu t waddrsu t waddrh dout0 t rc
altera corporation 6?31 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics figure 6?5. stratix gx transceiver reset & pll lock time waveform note (1) note to figure 6?5 : (1) waveforms are for minimum pulse width timing and output timing only. please refer to the stratix gx transceiver user guide for the complete reset sequence. tables 6?44 through 6?50 show the internal timing microparameters for all stratix gx devices. re g _data-out unre g _data-out rden rdaddress bn b0 doutn-2 doutn-1 dout n doutn-1 doutn t weresu t wereh t dataco1 t datac o 2 t rc table 6?44. le internal timing microparameters symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t su 10 10 11 ps t h 100 100 114 ps t co 156 176 202 ps t lut 366 459 527 ps t clr 100 100 114 ps t pre 100 100 114 ps t clkhl 100 100 114 ps
6?32 altera corporation stratix gx device handbook, volume 1 june 2006 timing model table 6?45. ioe internal timing microparameters symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t su 64 68 68 ps t h 76 80 80 ps t co 162 171 171 ps t pin2combout_r 1,038 1,093 1,256 ps t pin2combout_c 927 976 1,122 ps t combin2pin_r 2,944 3,099 3,563 ps t combin2pin_c 3,189 3,357 3,860 ps t clr 262 276 317 ps t pre 262 276 317 ps t clkhl 90 95 109 ps table 6?46. dsp block internal timing microparameters symbol -5 speed grade -6 speed grade -7 speed grade unit minmaxminmaxminmax t su 0 0 0 ps t h 67 75 86 ps t co 142 158 181 ps t inreg2pipe18 2,613 2,982 3,429 ps t inreg2pipe9 3,390 3,993 4,591 ps t pipe2outreg2add 2,002 2,203 2,533 ps t pipe2outreg4add 2,899 3,189 3,667 ps t pd9 3,709 4,081 4,692 ps t pd18 4,795 5,275 6,065 ps t pd36 7,495 8,245 9,481 ps t clr 450 500 575 ps t clkhl 1,350 1,500 1,724 ps
altera corporation 6?33 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics table 6?47. m512 block internal timing microparameters symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t m512rc 3,340 3,816 4,387 ps t m512wc 3,318 3,590 4,128 ps t m512weresu 110 123 141 ps t m512werh 34 38 43 ps t m512datasu 110 123 141 ps t m512datah 34 38 43 ps t m512waddrasu 110 123 141 ps t m512waddrh 34 38 43 ps t m512dataco1 424 472 541 ps t m512dataco2 3,366 3,846 4,421 ps t m512clkhl 150 167 192 ps t m512clr 170 189 217 ps table 6?48. m4k block internal timing microparameters (part 1 of 2) symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t m4krc 3,807 4,320 4,967 ps t m4kwc 2,556 2,840 3,265 ps t m4kweresu 131 149 171 ps t m4kwerh 34 38 43 ps t m4kdatasu 131 149 171 ps t m4kdatah 34 38 43 ps t m4kwaddrasu 131 149 171 ps t m4kwaddrh 34 38 43 ps t m4kraddrasu 131 149 171 ps t m4kraddrh 34 38 43 ps t m4kdatabsu 131 149 171 ps t m4kdatabh 34 38 43 ps t m4kaddrbsu 131 149 171 ps t m4kaddrbh 34 38 43 ps
6?34 altera corporation stratix gx device handbook, volume 1 june 2006 timing model t m4kdataco1 571 635 729 ps t m4kdataco2 3,984 4,507 5,182 ps t m4kclkhl 150 167 192 ps t m4kclr 170 189 255 ps table 6?49. m-ram block internal timing microparameters symbol -5 -6 -7 unit min max min max min max t mramrc 4,364 4,838 5,562 ps t mramwc 3,654 4,127 4,746 ps t mramweresu 25 25 28 ps t mramwerh 18 20 23 ps t mramdatasu 25 25 28 ps t mramdatah 18 20 23 ps t mramwaddrasu 25 25 28 ps t mramwaddrh 18 20 23 ps t mramraddrasu 25 25 28 ps t mramraddrh 18 20 23 ps t mramdatabsu 25 25 28 ps t mramdatabh 18 20 23 ps t mramaddrbsu 25 25 28 ps t mramaddrbh 18 20 23 ps t mramdataco1 1,038 1,053 1,210 ps t mramdataco2 4,362 4,939 5,678 ps t mramclkhl 270 300 345 ps t mramclr 135 150 172 ps table 6?48. m4k block internal timing microparameters (part 2 of 2) symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max
altera corporation 6?35 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics routing delays vary depending on the load on a specific routing line. the quartus ii software reports the routing delay information when running the timing analysis for a design. contact altera applications engineering for more details. external timing parameters external timing parameters are specified by device density and speed grade. figure 6?6 shows the timing model for bidirectional ioe pin timing. all registers are within the ioe. table 6?50. stratix gx transceiver reset & pll lock time parameters symbol min typ max units t analogresetpw (5) 1ms t digitalresetpw (5) 4 parallel clock cycle t tx_pll_lock (3) 10 s t rx_freqlock (4) 5ms t rx_freqlock2phaselock (2) 5s notes to table 6?50 : (1) the minimum pulse width specified is asso ciated with the power-down of circuits. (2) the clock recovery unit (cru) phase locked-to-data time is based on a data rate of 500 mbps and 8b/10b encoded data. (3) after #pll_areset , pll_enable , or pll power-up, the time required for the transceiver pll to lock to the reference clock. (4) after #rx_analogreset , the time for the cru to switch to lock-to-data mode. (5) there is no maximum pulse width specificatio n. the gxb can be held in reset indefinitely.
6?36 altera corporation stratix gx device handbook, volume 1 june 2006 timing model figure 6?6. external timing in stratix gx devices all external i/o timing parameters shown are for 3.3-v lvttl or lvcmos i/o standards with the maximum current strength. for external i/o timing us ing standards other than lvttl or lvcmos use the i/o standard input and output delay adders in tables 6?72 through 6?76 . table 6?51 shows the external i/o timing parameters when using fast regional clock networks. prn clrn dq prn clrn dq prn clrn dq dedicated clock bidirectional pin output register input register oe register t insu t inh t outco table 6?51. stratix gx fast regional clock external i/o timing parameters notes (1) , (2) symbol parameter conditions t insu setup time for input or bidire ctional pin using column ioe input register with fast regional clock fed by fclk pin t inh hold time for input or bidire ctional pin using column ioe input register with fast regional clock fed by fclk pin t outco clock-to-output delay output or bidirectional pin using column ioe output register with fast regional clock fed by fclk pin c load = 10 pf notes to table 6?51 : (1) these timing parameters are sample-tested only. (2) these timing parameters are for column ioe pins. row ioe pins are 100- to 250-ps slower depending on device and speed grade and whether it is t co or t su . you should use the quartus ii softwa re to verify the external timing for any pin.
altera corporation 6?37 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics table 6?52 shows the external i/o timing parameters when using regional clock networks. table 6?53 shows the external i/o timing parameters when using global clock networks. table 6?52. stratix gx regional clock external i/o timing parameters notes (1) , (2) symbol parameter conditions t insu setup time for input or bidire ctional pin using column ioe input register with regional clock fed by clk pin t inh hold time for input or bidire ctional pin using column ioe input register with regional clock fed by clk pin t outco clock-to-output delay output or bidirectional pin using column ioe output register with regional clock fed by clk pin c load = 10 pf t insupll setup time for input or bidire ctional pin using column ioe input register with regional cl ock fed by enhanced pll with default phase setting t inhpll hold time for input or bidire ctional pin using column ioe input register with regional cl ock fed by enhanced pll with default phase setting t outcopll clock-to-output delay output or bidirectional pin using column ioe output register with regional clock enhanced pll with default phase setting c load = 10 pf notes to table 6?52 : (1) these timing parameters are sample-tested only. (2) these timing parameters are for column ioe pins. row ioe pins are 100- to 250-ps slower depending on device, speed grade, and the specific parameter in question. you should use the quartus ii software to verify the external timing for any pin. table 6?53. stratix gx global clock external i/o timing parameters (part 1 of 2) notes (1) , (2) symbol parameter conditions t insu setup time for input or bidire ctional pin using column ioe input register with global clock fed by clk pin t inh hold time for input or bidire ctional pin using column ioe input register with global clock fed by clk pin t outco clock-to-output delay output or bidirectional pin using column ioe output register with global clock fed by clk pin c load = 10 pf t insupll setup time for input or bidire ctional pin using column ioe input register with global cl ock fed by enhanced pll with default phase setting
6?38 altera corporation stratix gx device handbook, volume 1 june 2006 timing model tables 6?54 through 6?59 show the external timing parameters on column and row pins for ep1sgx10 devices. t inhpll hold time for input or bidire ctional pin using column ioe input register with global clock fed by enhanced pll with default phase setting t outcopll clock-to-output delay output or bidirectional pin using column ioe output register with global clock enhanced pll with default phase setting c load = 10 pf notes to table 6?53 : (1) these timing parameters are sample-tested only. (2) these timing parameters are for column ioe pins. row ioe pins are 100- to 250-ps slower depending on device, speed grade, and the specific parameter in question. you should use the quartus ii software to verify the external timing for any pin. table 6?53. stratix gx global clock external i/o timing parameters (part 2 of 2) notes (1) , (2) symbol parameter conditions table 6?54. ep1sgx10 column pin fast regional clock external i/o timing parameters symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t insu 2.245 2.332 2.666 ns t inh 0.000 0.000 0.000 ns t outco 2.000 4.597 2.000 4.920 2.000 5.635 ns table 6?55. ep1sgx10 column pin regional clock external i/o timing parameters symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t insu 2.114 2.218 2.348 ns t inh 0.000 0.000 0.000 ns t outco 2.000 4.728 2.000 5.078 2.000 6.004 ns t insupll 1.035 0.941 1.070 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 2.629 0.500 2.769 0.500 3.158 ns
altera corporation 6?39 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics table 6?56. ep1sgx10 column pin global cl ock external i/o timing parameters symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t insu 1.785 1.814 2.087 ns t inh 0.000 0.000 0.000 ns t outco 2.000 5.057 2.000 5.438 2.000 6.214 ns t insupll 0.988 0.936 1.066 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 2.634 0.500 2.774 0.500 3.162 ns table 6?57. ep1sgx10 row pin fast regional clock external i/o timing parameters symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t insu 2.194 2.384 2.727 ns t inh 0.000 0.000 0.000 ns t outco 2.000 4.956 2.000 4.971 2.000 5.463 ns table 6?58. ep1sgx10 row pin regional cl ock external i/o timing parameters symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t insu 2.244 2.413 2.574 ns t inh 0.000 0.000 0.000 ns t outco 2.000 4.906 2.000 4.942 2.000 5.616 ns t insupll 1.126 1.186 1.352 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 2.804 0.500 2.627 0.500 2.765 ns table 6?59. ep1sgx10 row pin global clock exte rnal i/o timing parameters (part 1 of 2) symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t insu 1.919 2.062 2.368 ns t inh 0.000 0.000 0.000 ns
6?40 altera corporation stratix gx device handbook, volume 1 june 2006 timing model tables 6?60 through 6?65 show the external timing parameters on column and row pins for ep1sgx25 devices. t outco 2.000 5.231 2.000 5.293 2.000 5.822 ns t insupll 1.126 1.186 1.352 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 2.804 0.500 2.627 0.500 2.765 ns table 6?59. ep1sgx10 row pin global clock exte rnal i/o timing parameters (part 2 of 2) symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max table 6?60. ep1sgx25 column pin fast regional clock external i/o timing parameters symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t insu 2.418 2.618 3.014 ns t inh 0.000 0.000 0.000 ns t outco 2.000 4.524 2.000 4.834 2.000 5.538 ns table 6?61. ep1sgx25 column pin regional clock external i/o timing parameters symbol -5 speed grade -6 speed grade -7 speed grade unit minmaxminmaxminmax t insu 1.713 1.838 2.069 ns t inh 0.000 0.000 0.000 ns t outco 2.000 5.229 2.000 5.614 2.000 6.432 ns t insupll 1.061 1.155 1.284 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 2.661 0.500 2.799 0.500 3.195 ns
altera corporation 6?41 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics table 6?62. ep1sgx25 column pin global cl ock external i/o timing parameters symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t insu 1.790 1.883 2.120 ns t inh 0.000 0.000 0.000 ns t outco 2.000 5.194 2.000 5.569 2.000 6.381 ns t insupll 1.046 1.141 1.220 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 2.676 0.500 2.813 0.500 3.208 ns table 6?63. ep1sgx25 row pin fast regional clock external i/o timing parameters symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t insu 2.394 2.594 2.936 ns t inh 0.000 0.000 0.000 ns t outco 2.000 4.456 2.000 4.761 2.000 5.454 ns table 6?64. ep1sgx25 row pin regional cl ock external i/o timing parameters symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t insu 1.970 2.109 2.377 ns t inh 0.000 0.000 0.000 ns t outco 2.000 4.880 2.000 5.246 2.000 6.013 ns t insupll 1.326 1.386 1.552 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 2.304 0.500 2.427 0.500 2.765 ns table 6?65. ep1sgx25 row pin global clock exte rnal i/o timing parameters (part 1 of 2) symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t insu 1.963 2.108 2.379 ns t inh 0.000 0.000 0.000 ns
6?42 altera corporation stratix gx device handbook, volume 1 june 2006 timing model tables 6?66 through 6?71 show the external timing parameters on column and row pins for ep1sgx40 devices. t outco 2.000 4.887 2.000 5.247 2.000 6.011 ns t insupll 1.326 1.386 1.552 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 2.304 0.500 2.427 0.500 2.765 ns table 6?65. ep1sgx25 row pin global clock exte rnal i/o timing parameters (part 2 of 2) symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max table 6?66. ep1sgx40 column pin fast regional clock external i/o timing parameters symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t insu 2.704 2.912 3.235 ns t inh 0.000 0.000 0.000 ns t outco 2.000 5.060 2.000 5.432 2.000 6.226 ns table 6?67. ep1sgx40 column pin regional clock external i/o timing parameters symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t insu 2.467 2.671 3.011 ns t inh 0.000 0.000 0.000 ns t outco 2.000 5.255 2.000 5.673 2.000 6.501 ns t insupll 1.254 1.259 1.445 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 2.610 0.500 2.751 0.500 3.134 ns
altera corporation 6?43 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics table 6?68. ep1sgx40 column pin global cl ock external i/o timing parameters symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t insu 2.033 2.184 2.451 ns t inh 0.000 0.000 0.000 ns t outco 2.000 5.689 2.000 6.116 2.000 7.010 ns t insupll 1.228 1.278 1.415 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 2.594 0.500 2.732 0.500 3.113 ns table 6?69. ep1sgx40 row pin fast regional clock external i/o timing parameters symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t insu 2.450 2.662 3.046 ns t inh 0.000 0.000 0.000 ns t outco 2.000 4.880 2.000 5.241 2.000 6.004 ns table 6?70. ep1sgx40 row pin regional cl ock external i/o timing parameters symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t insu 2.398 2.567 2.938 ns t inh 0.000 0.000 0.000 ns t outco 2.000 4.932 2.000 5.336 2.000 6.112 ns t insupll 1.126 1.186 1.352 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 2.304 0.500 2.427 0.500 2.765 ns table 6?71. ep1sgx40 row pin global clock exte rnal i/o timing parameters (part 1 of 2) symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max t insu 1.965 2.128 2.429 ns t inh 0.000 0.000 0.000 ns
6?44 altera corporation stratix gx device handbook, volume 1 june 2006 timing model external i/o delay parameters external i/o delay timing parameters , both for i/o standard input and output adders and programmable input and output delays, are specified by speed grade, independent of device density. tables 6?72 through 6?77 show the adder delays associated with column and row i/o pins. if an i/o standard is selected other than lvttl 24 ma with a fast slew rate, add the selected delay to the external t co and t su i/o parameters. t outco 2.000 5.365 2.000 5.775 2.000 6.621 ns t insupll 1.126 1.186 1.352 ns t inhpll 0.000 0.000 0.000 ns t outcopll 0.500 2.304 0.500 2.427 0.500 2.765 ns table 6?71. ep1sgx40 row pin global clock exte rnal i/o timing parameters (part 2 of 2) symbol -5 speed grade -6 speed grade -7 speed grade unit min max min max min max table 6?72. stratix gx i/o standard column pin input delay adders (part 1 of 2) i/o standard -5 speed grade -6 speed grade -7 speed grade unit min max min max min max lvcmos 0 0 0 ps 3.3-v lvttl 0 0 0 ps 2.5-v lvttl 30 31 35 ps 1.8-v lvttl 150 157 180 ps 1.5-v lvttl 210 220 252 ps gtl 220 231 265 ps gtl+ 220 231 265 ps 3.3-v pci 0 0 0 ps 3.3-v pci-x 1.0 0 0 0 ps compact pci 0 0 0 ps agp 1 0 0 0 ps agp 2 0 0 0 ps ctt 120 126 144 ps sstl-3 class i ?30 ?32 ?37 ps sstl-3 class ii ?30 ?32 ?37 ps
altera corporation 6?45 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics sstl-2 class i ?70 ?74 ?86 ps sstl-2 class ii ?70 ?74 ?86 ps sstl-18 class i 180 189 217 ps sstl-18 class ii 180 189 217 ps 1.5-v hstl class i 120 126 144 ps 1.5-v hstl class ii 120 126 144 ps 1.8-v hstl class i 70 73 83 ps 1.8-v hstl class ii 70 73 83 ps table 6?73. stratix gx i/o standard row pin input delay adders (part 1 of 2) i/o standard -5 speed grade -6 speed grade -7 speed grade unit min max min max min max lvcmos 0 0 0 ps 3.3-v lvttl 0 0 0 ps 2.5-v lvttl 30 31 35 ps 1.8-v lvttl 150 157 180 ps 1.5-v lvttl 210 220 252 ps gtl 0 0 0 ps gtl+ 220 231 265 ps 3.3-v pci 0 0 0 ps 3.3-v pci-x 1.0 0 0 0 ps compact pci 0 0 0 ps agp 1 0 0 0 ps agp 2 0 0 0 ps ctt 80 84 96 ps sstl-3 class i ?30 ?32 ?37 ps sstl-3 class ii ?30 ?32 ?37 ps sstl-2 class i ?70 ?74 ?86 ps sstl-2 class ii ?70 ?74 ?86 ps sstl-18 class i 180 189 217 ps sstl-18 class ii 0 0 0 ps 1.5-v hstl class i 130 136 156 ps table 6?72. stratix gx i/o standard column pin input delay adders (part 2 of 2) i/o standard -5 speed grade -6 speed grade -7 speed grade unit min max min max min max
6?46 altera corporation stratix gx device handbook, volume 1 june 2006 timing model 1.5-v hstl class ii 0 0 0 ps 1.8-v hstl class i 70 73 83 ps 1.8-v hstl class ii 70 73 83 ps lv d s (1) 40 42 48 ps lvpecl (1) ?50 ?53 ?61 ps 3.3-v pcml (1) 330 346 397 ps hypertransport (1) 80 84 96 ps table 6?74. stratix gx i/o standard out put delay adders for fast slew rate on column pins (part 1 of 2) standard -5 speed grade -6 speed grade -7 speed grade unit min max min max min max lvcmos 2 ma 570 599 689 ps 4 ma 570 599 689 ps 8 ma 350 368 423 ps 12 ma 130 137 157 ps 24 ma 0 0 0 ps 3.3-v lvttl 4 ma 570 599 689 ps 8 ma 350 368 423 ps 12 ma 130 137 157 ps 16 ma 70 74 85 ps 24 ma 0 0 0 ps 2.5-v lvttl 2 ma 830 872 1,002 ps 8 ma 250 263 302 ps 12 ma 140 147 169 ps 16 ma 100 105 120 ps 1.8-v lvttl 2 ma 420 441 507 ps 8 ma 350 368 423 ps 12 ma 350 368 423 ps 1.5-v lvttl 2 ma 1,740 1,827 2,101 ps 4 ma 1,160 1,218 1,400 ps 8 ma 690 725 833 ps gtl ?150 ?157 ?181 ps table 6?73. stratix gx i/o standard row pin input delay adders (part 2 of 2) i/o standard -5 speed grade -6 speed grade -7 speed grade unit min max min max min max
altera corporation 6?47 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics gtl+ ?110 ?115 ?133 ps 3.3-v pci ?230 ?241 ?277 ps 3.3-v pci-x 1.0 ?230 ?241 ?277 ps compact pci ?230 ?241 ?277 ps agp 1 ?30 ?31 ?36 ps agp 2 ?30 ?31 ?36 ps ctt 50 53 61 ps sstl-3 class i 90 95 109 ps sstl-3 class ii ?50 ?52 ?60 ps sstl-2 class i 100 105 120 ps sstl-2 class ii 20 21 24 ps sstl-18 class i 230 242 278 ps sstl-18 class ii 0 0 0 ps 1.5-v hstl class i 380 399 459 ps 1.5-v hstl class ii 190 200 230 ps 1.8-v hstl class i 380 399 459 ps 1.8-v hstl class ii 390 410 471 ps table 6?75. stratix gx i/o standard output delay adders for fast slew rate on row pins (part 1 of 2) standard -5 speed grade -6 speed grade -7 speed grade unit min max min max min max lvcmos 2 ma 570 599 689 ps 4 ma 570 599 689 ps 8 ma 350 368 423 ps 12 ma 130 137 157 ps 24 ma 0 0 0 ps 3.3-v lvttl 4 ma 570 599 689 ps 8 ma 350 368 423 ps 12 ma 130 137 157 ps 16 ma 70 74 85 ps 24 ma 0 0 0 ps table 6?74. stratix gx i/o standard out put delay adders for fast slew rate on column pins (part 2 of 2) standard -5 speed grade -6 speed grade -7 speed grade unit min max min max min max
6?48 altera corporation stratix gx device handbook, volume 1 june 2006 timing model 2.5-v lvttl 2 ma 830 872 1,002 ps 8 ma 250 263 302 ps 12 ma 140 147 169 ps 16 ma 100 105 120 ps 1.8-v lvttl 2 ma 1,510 1,586 1,824 ps 8 ma 420 441 507 ps 12 ma 350 368 423 ps 1.5-v lvttl 2 ma 1,740 1,827 2,101 ps 4 ma 1,160 1,218 1,400 ps 8 ma 690 725 833 ps ctt 50 53 61 ps sstl-3 class i 90 95 109 ps sstl-3 class ii ?50 ?52 ?60 ps sstl-2 class i 100 105 120 ps sstl-2 class ii 20 21 24 ps lv d s (1) ?20 ?21 ?24 ps lvpecl (1) 40 42 48 ps pcml (1) ?60 ?63 ?73 ps hypertransport technology (1) 70 74 85 ps table 6?76. stratix gx i/o standard output delay adders for slow slew rate on column pins (part 1 of 2) i/o standard -5 speed grade -6 speed grade -7 speed grade unit min max min max min max lvcmos 2 ma 1,911 2,011 2,312 ps 4 ma 1,911 2,011 2,312 ps 8 ma 1,691 1,780 2,046 ps 12 ma 1,471 1,549 1,780 ps 24 ma 1,341 1,412 1,623 ps table 6?75. stratix gx i/o standard output delay adders for fast slew rate on row pins (part 2 of 2) standard -5 speed grade -6 speed grade -7 speed grade unit min max min max min max
altera corporation 6?49 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics 3.3-v lvttl 4 ma 1,993 2,097 2,411 ps 8 ma 1,773 1,866 2,145 ps 12 ma 1,553 1,635 1,879 ps 16 ma 1,493 1,572 1,807 ps 24 ma 1,423 1,498 1,722 ps 2.5-v lvttl 2 ma 2,631 2,768 3,182 ps 8 ma 2,051 2,159 2,482 ps 12 ma 1,941 2,043 2,349 ps 16 ma 1,901 2,001 2,300 ps 1.8-v lvttl 2 ma 4,632 4,873 5,604 ps 8 ma 3,542 3,728 4,287 ps 12 ma 3,472 3,655 4,203 ps 1.5-v lvttl 2 ma 6,620 6,964 8,008 ps 4 ma 6,040 6,355 7,307 ps 8 ma 5,570 5,862 6,740 ps gtl 1,191 1,255 1,442 ps gtl+ 1,231 1,297 1,90 ps 3.3-v pci 1,111 1,171 1,346 ps 3.3-v pci-x 1.0 1,111 1,171 1,346 ps compact pci 1,111 1,171 1,346 ps agp 1 1,311 1,381 1,587 ps agp 2 1,311 1,381 1,587 ps ctt 1,391 1,465 1,684 ps sstl-3 class i 1,431 1,507 1,732 ps sstl-3 class ii 1,291 1,360 1,563 ps sstl-2 class i 1,912 2,013 2,314 ps sstl-2 class ii 1,832 1,929 2,218 ps sstl-18 class i 3,097 3,260 3,748 ps sstl-18 class ii 2,867 3,018 3,470 ps 1.5-v hstl class i 4,916 5,174 5,950 ps 1.5-v hstl class ii 4,726 4,975 5,721 ps 1.8-v hstl class i 3,247 3,417 3,929 ps 1.8-v hstl class ii 3,257 3,428 3,941 ps table 6?76. stratix gx i/o standard output delay adders for slow slew rate on column pins (part 2 of 2) i/o standard -5 speed grade -6 speed grade -7 speed grade unit min max min max min max
6?50 altera corporation stratix gx device handbook, volume 1 june 2006 timing model table 6?77. stratix gx i/o standard output delay adders for slow slew rate on row pins i/o standard -5 speed grade -6 speed grade -7 speed grade unit min max min max min max lvcmos 2 ma 1,930 2,031 2,335 ps 4 ma 1,930 2,031 2,335 ps 8 ma 1,710 1,800 2,069 ps 12 ma 1,490 1,569 1,803 ps 3.3-v lvttl 4 ma 1,953 2,055 2,363 ps 8 ma 1,733 1,824 2,097 ps 12 ma 1,513 1,593 1,831 ps 16 ma 1,453 1,530 1,759 ps 2.5-v lvttl 2 ma 2,632 2,769 3,183 ps 8 ma 2,052 2,160 2,483 ps 12 ma 1,942 2,044 2,350 ps 16 ma 1,902 2,002 2,301 ps 1.8-v lvttl 2 ma 4,537 4,773 5,489 ps 8 ma 3,447 3,628 4,172 ps 12 ma 3,377 3,555 4,088 ps 1.5-v lvttl 2 ma 6,575 6,917 7,954 ps 4 ma 5,995 6,308 7,253 ps 8 ma 5,525 5,815 6,686 ps ctt 1,410 1,485 1,707 ps sstl-3 class i 1,450 1,527 1,755 ps sstl-3 class ii 1,310 1,380 1,586 ps sstl-2 class i 1,797 1,892 2,175 ps sstl-2 class ii 1,717 1,808 2,079 ps lv d s (1) 1,340 1,411 1,622 ps lvpecl (1) 1,400 1,474 1,694 ps 3.3-v pcml (1) 1,300 1,369 1,573 ps hypertransport technology (1) 1,430 1,506 1,731 ps note to tables 6?72 through 6?77 : (1) these parameters are only availa ble on the left side row i/o pins.
altera corporation 6?51 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics tables 6?78 and 6?79 show the adder delays for the column and row ioe programmable delays, respectively. these delays are controlled with the quartus ii software logic options listed in the parameter column. table 6?78. stratix gx ioe programmable delays on column pins parameter setting -5 speed grade -6 speed grade -7 speed grade unit min max min max min max decrease input delay to internal cells off 3,970 4,367 5,022 ps on 3,390 3,729 4,288 ps small 2,810 3,091 3,554 ps medium 212 224 257 ps large 212 224 257 ps decrease input delay to input register off 3900 4,290 4,933 ps on 0 0 0 ps decrease input delay to output register off 1,240 1,364 1,568 ps on 0 0 0 ps increase delay to output pin off 0 0 0 ps on 377 397 456 ps increase delay to output enable pin off 0 0 0 ps on 338 372 427 ps increase output clock enable delay off 0 0 0 ps on 540 594 683 ps small 1,016 1,118 1,285 ps large 1,016 1,118 1,285 ps increase input clock enable delay off 0 0 0 ps on 540 594 683 ps small 1,016 1,118 1,285 ps large 1,016 1,118 1,285 ps increase output enable clock enable delay off 0 0 0 ps on 540 594 683 ps small 1,016 1,118 1,285 ps large 1,016 1,118 1,285 ps
6?52 altera corporation stratix gx device handbook, volume 1 june 2006 timing model table 6?79. stratix gx ioe programmable delays on row pins parameter setting -5 speed grade -6 speed grade -7 speed grade unit minmaxminmaxminmax decrease input delay to internal cells off 3,970 4,367 5,022 ps on 3,390 3,729 4,288 ps small 2,810 3,091 3,554 ps medium 164 173 198 ps large 164 173 198 ps decrease input delay to input register off 3,900 4,290 4,933 ps on 0 0 0 ps decrease input delay to output register off 1,240 1,364 1,568 ps on 0 0 0 ps increase delay to output pin off 0 0 0 ps on 377 397 456 ps increase delay to output enable pin off 0 0 0 ps on 348 383 441 ps increase output clock enable delay off 0 0 0 ps on 180 198 227 ps small 260 286 328 ps large 260 286 328 ps increase input clock enable delay off 0 0 0 ps on 180 198 227 ps small 260 286 328 ps large 260 286 328 ps increase output enable clock enable delay off 0 0 0 ps on 540 594 683 ps small 1,016 1,118 1,285 ps large 1,016 1,118 1,285 ps
altera corporation 6?53 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics the scaling factors for output pin timing in table 6?80 are shown in units of time per pf unit of capacita nce (ps/pf). add this delay to the combinational timing path for output or bidirectional pins in addition to the ?i/o adder? delays shown in tables 6?72 through 6?77 and the ?ioe programmable delays? in tables 6?78 and 6?79 . table 6?80. output delay adder for loadi ng on lvttl/lvcmos output buffers lvttl/lvcmos standards conditions output pin adder delay (ps/pf) parameter value 3.3-v lvttl 2.5-v lvttl 1.8-v lvttl 1.5-v lvttl lvcmos drive strength 24 ma 15 ? ? - 8 16 ma 25 18 ? ? ? 12 ma 30 25 25 ? 15 8ma 50 35 40 35 20 4ma 60 ? ? 80 30 2 ma ? 75 120 160 60 sstl/hstl standards conditions output pin adder delay (ps/pf) sstl-3 sstl-2 sstl-1.8 1.5-v hstl 1.8-v hstl class i class ii 25 25 25 25 25 25 20 25 20 20 gtl+/gtl/ctt/pci standards conditions output pin adder delay (ps/pf) parameter value gtl+ gtl ctt pci agp v ccio voltage level 3.3 v 18 18 25 20 20 2.5 v 15 18 - - -
6?54 altera corporation stratix gx device handbook, volume 1 june 2006 timing model maximum input & output clock rates tables 6?81 through 6?83 show the maximum input clock rate for column and row pins in stratix gx devices. table 6?81. stratix gx maximum input clock rate for clk[7..4] & clk[15..12] pins i/o standard -5 speed grade -6 speed grade -7 speed grade unit lvttl 422 422 390 mhz 2.5 v 422 422 390 mhz 1.8 v 422 422 390 mhz 1.5 v 422 422 390 mhz lvcmos 422 422 390 mhz gtl 300 250 200 mhz gtl+ 300 250 200 mhz sstl-3 class i 400 350 300 mhz sstl-3 class ii 400 350 300 mhz sstl-2 class i 400 350 300 mhz sstl-2 class ii 400 350 300 mhz sstl-18 class i 400 350 300 mhz sstl-18 class ii 400 350 300 mhz 1.5-v hstl class i 400 350 300 mhz 1.5-v hstl class ii 400 350 300 mhz 1.8-v hstl class i 400 350 300 mhz 1.8-v hstl class ii 400 350 300 mhz 3.3-v pci 422 422 390 mhz 3.3-v pci-x 1.0 422 422 390 mhz compact pci 422 422 390 mhz agp 1 422 422 390 mhz agp 2 422 422 390 mhz ctt 300 250 200 mhz differential hstl 400 350 300 mhz lvds 645 645 622 mhz lvpecl 645 645 622 mhz pcml 300 275 275 mhz hypertransport technology 500 500 450 mhz
altera corporation 6?55 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics table 6?82. stratix gx maximum input clock rate for clk[0, 2, 9, 11] pins & fpll[8..7]clk pins i/o standard -5 speed grade -6 speed grade -7 speed grade unit lvttl 422 422 390 mhz 2.5 v 422 422 390 mhz 1.8 v 422 422 390 mhz 1.5 v 422 422 390 mhz lvcmos 422 422 390 mhz gtl 300 250 200 mhz gtl+ 300 250 200 mhz sstl-3 class i 400 350 300 mhz sstl-3 class ii 400 350 300 mhz sstl-2 class i 400 350 300 mhz sstl-2 class ii 400 350 300 mhz sstl-18 class i 400 350 300 mhz sstl-18 class ii 400 350 300 mhz 1.5-v hstl class i 400 350 300 mhz 1.5-v hstl class ii 400 350 300 mhz 1.8-v hstl class i 400 350 300 mhz 1.8-v hstl class ii 400 350 300 mhz 3.3-v pci 422 422 390 mhz 3.3-v pci-x 1.0 422 422 390 mhz compact pci 422 422 390 mhz agp 1 422 422 390 mhz agp 2 422 422 390 mhz ctt 300 250 200 mhz differential hstl 400 350 300 mhz lvds 717 717 640 mhz lvpecl 717 717 640 mhz pcml 400 375 350 mhz hypertransport technology 717 717 640 mhz table 6?83. stratix gx maximum input clock rate for clk[1, 3, 8, 10] pins (part 1 of 2) i/o standard -5 speed grade -6 speed grade -7 speed grade unit lvttl 422 422 390 mhz 2.5 v 422 422 390 mhz
6?56 altera corporation stratix gx device handbook, volume 1 june 2006 timing model tables 6?84 and 6?85 show the maximum output clock rate for column and row pins in stratix gx devices. 1.8 v 422 422 390 mhz 1.5 v 422 422 390 mhz lvcmos 422 422 390 mhz gtl 300 250 200 mhz gtl+ 300 250 200 mhz sstl-3 class i 400 350 300 mhz sstl-3 class ii 400 350 300 mhz sstl-2 class i 400 350 300 mhz sstl-2 class ii 400 350 300 mhz sstl-18 class i 400 350 300 mhz sstl-18 class ii 400 350 300 mhz 1.5-v hstl class i 400 350 300 mhz 1.5-v hstl class ii 400 350 300 mhz 1.8-v hstl class i 400 350 300 mhz 1.8-v hstl class ii 400 350 300 mhz 3.3-v pci 422 422 390 mhz 3.3-v pci-x 1.0 422 422 390 mhz compact pci 422 422 390 mhz agp 1 422 422 390 mhz agp 2 422 422 390 mhz ctt 300 250 200 mhz differential hstl 400 350 300 mhz lvds 645 645 640 mhz lvpecl 645 645 640 mhz pcml 300 275 275 mhz hypertransport technology 645 645 640 mhz table 6?83. stratix gx maximum input clock rate for clk[1, 3, 8, 10] pins (part 2 of 2) i/o standard -5 speed grade -6 speed grade -7 speed grade unit table 6?84. stratix gx maximum output clock rate for pll[5, 6, 11, 12] pins (part 1 of 2) i/o standard -5 speed grade -6 speed grade -7 speed grade unit lvttl 350 300 250 mhz 2.5 v 350 300 300 mhz
altera corporation 6?57 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics 1.8 v 250 250 250 mhz 1.5 v 225 200 200 mhz lvcmos 350 300 250 mhz gtl 200 167 125 mhz gtl+ 200 167 125 mhz sstl-3 class i 167 150 133 mhz sstl-3 class ii 167 150 133 mhz sstl-2 class i 200 200 167 mhz sstl-2 class ii 200 200 167 mhz sstl-18 class i 150 133 133 mhz sstl-18 class ii 150 133 133 mhz 1.5-v hstl class i 250 225 200 mhz 1.5-v hstl class ii 225 200 200 mhz 1.8-v hstl class i 250 225 200 mhz 1.8-v hstl class ii 225 200 200 mhz 3.3-v pci 350 300 250 mhz 3.3-v pci-x 1.0 350 300 250 mhz compact pci 350 300 250 mhz agp 1 350 300 250 mhz agp 2 350 300 250 mhz ctt 200 200 200 mhz differential hstl 225 200 200 mhz differential sstl-2 200 200 167 mhz lvds 500 500 500 mhz lvpecl 500 500 500 mhz pcml 350 350 350 mhz hypertransport technology 350 350 350 mhz table 6?85. stratix gx maximum output clock rate (u sing i/o pins) for pll[1, 2] pins (part 1 of 2) i/o standard -5 speed grade -6 speed grade -7 speed grade unit lvttl 400 350 300 mhz 2.5 v 400 350 300 mhz 1.8 v 400 350 300 mhz table 6?84. stratix gx maximum output clock rate for pll[5, 6, 11, 12] pins (part 2 of 2) i/o standard -5 speed grade -6 speed grade -7 speed grade unit
6?58 altera corporation stratix gx device handbook, volume 1 june 2006 high-speed i/o specification high-speed i/o specification table 6?86 provides high-speed timing specifications definitions. 1.5 v 350 300 300 mhz lvcmos 400 350 300 mhz gtl 200 167 125 mhz gtl+ 200 167 125 mhz sstl-3 class i 167 150 133 mhz sstl-3 class ii 167 150 133 mhz sstl-2 class i 150 133 133 mhz sstl-2 class ii 150 133 133 mhz sstl-18 class i 150 133 133 mhz sstl-18 class ii 150 133 133 mhz hstl class i 250 225 200 mhz hstl class ii 225 225 200 mhz 3.3-v pci 250 225 200 mhz 3.3-v pci-x 1.0 225 225 200 mhz compact pci 400 350 300 mhz agp 1 400 350 300 mhz agp 2 400 350 300 mhz ctt 300 250 200 mhz differential hstl 225 225 200 mhz lvds 717 717 500 mhz lvpecl 717 717 500 mhz pcml 420 420 420 mhz hypertransport technology 420 420 420 mhz table 6?85. stratix gx maximum output clock rate (u sing i/o pins) for pll[1, 2] pins (part 2 of 2) i/o standard -5 speed grade -6 speed grade -7 speed grade unit table 6?86. high-speed timing specifica tions & definitions (part 1 of 2) high-speed timing specification definitions t c high-speed receiver/transmitter input and output clock period. f hsclk high-speed receiver/transmitter input and output clock frequency. t rise low-to-high transmission time.
altera corporation 6?59 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics table 6?87 shows the high-speed i/o timing specifications for stratix gx devices. t fall high-to-low transmission time. timing unit interval (tui) the timing budget allowed for skew, propagation delays, and data sampling window. (tui = 1/(receiver input clock frequency multiplication factor) = t c / w ). f hsdr maximum/minimum lvds data transfer rate (f hsdr = 1/tui), non-dpa. f hsdrdpa maximum/minimum lvds data transfer rate (f hsdrdpa = 1/tui), dpa. channel-to-channel skew (tccs) the timing differenc e between the fastest and slowest output edges, including t co variation and clock skew. the clock is included in the tccs measurement. sampling window (sw) the period of time during whic h the data must be valid in order to capture it correctly. the setup and hold times determine the ideal strobe position within the sampling window. sw = t sw (max) ? t sw (min). input jitter (peak-to-peak) peak-to-p eak input jitter on high-speed plls. output jitter (peak-to-peak) peak-to-p eak output jitter on high-speed plls. t duty duty cycle on high-speed transmitter output clock. t lock lock time for high-speed transmitter and receiver plls. table 6?86. high-speed timing specifica tions & definitions (part 2 of 2) high-speed timing specification definitions table 6?87. high-speed i/o s pecifications (part 1 of 4) notes (1) , (2) symbol conditions -5 speed grade -6 speed grade -7 speed grade unit min typ max min typ max min typ max f hsclk (clock frequency) (lvds, lvpecl, hypertransport technology) f hsclk = f hsdr / w w = 1 to 30 for 717 mbps w = 2 to 30 for > 717 mbps 10 717 10 717 10 624 mhz f hsclk_dpa 74 717 74 717 74 717 mhz
6?60 altera corporation stratix gx device handbook, volume 1 june 2006 high-speed i/o specification f hsdr device operation (lvds, lvpecl, hypertransport technology) j = 10 300 840 300 840 300 840 mbps j = 8 300 840 300 840 300 840 mbps j = 7 300 840 300 840 300 840 mbps j = 4 300 840 300 840 300 840 mbps j = 2 100 624 100 624 100 462 mbps j = 1 (lvds and lvpecl only) 100 462 100 462 100 462 mbps f hsdrdpa (lvds, lvpecl) j=10 300 1000 300 840 300 840 mbps j=8 300 1000 300 840 300 840 mbps f hsclk (clock frequency) (pcml) f hsclk = f hsdr / w w = 1 to 30 10 400 10 400 10 311 mhz f hsdr device operation (pcml) j = 10 300 400 300 400 300 311 mbps j = 8 300 400 300 400 300 311 mbps j = 7 300 400 300 400 300 311 mbps j = 4 300 400 300 400 300 311 mbps j = 2 100 400 100 400 100 300 mbps j = 1 100 250 100 250 100 200 mbps dpa run length 6400 6400 6400 ui dpa jitter tolerance (p-p) all data rates 0.44 0.44 0.44 ui dpa minimum eye opening (p-p) 0.56 0.56 0.56 ui dpa receiver latency 595959 (3) table 6?87. high-speed i/o s pecifications (part 2 of 4) notes (1) , (2) symbol conditions -5 speed grade -6 speed grade -7 speed grade unit min typ max min typ max min typ max
altera corporation 6?61 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics dpa lock time standard train ing patt ern tr a n s ition den- sity spi-4, csix 0000 0000 0011 1111 1111 10% 256 256 256 (4) rapid io 0000 1111 25% 256 256 256 (4) 1001 0000 50% 256 256 256 (4) misc 1010 1010 100 % 256 256 256 (4) 0101 0101 256 256 256 (4) tccs all 200 200 300 ps sw pcml ( j = 4, 7, 8, 10) 750 750 800 ps pcml ( j = 2) 900 900 1,200 ps pcml ( j = 1) 1,500 1,500 1,700 ps lvds and lvpecl ( j =1) 500 500 550 ps lvds, lvpecl, hypertransport technology ( j =2 through 10) 440 440 500 ps input jitter tolerance (peak-to-peak) all 250 250 250 ps output jitter (peak-to-peak) all 160 160 200 ps output t rise lvds 80 110 120 80 110 120 80 110 120 ps hypertransport technology 110 170 200 110 170 200 120 170 200 ps lvpecl 90 130 150 90 130 150 100 135 150 ps pcml 80 110 135 80 110 135 80 110 135 ps table 6?87. high-speed i/o s pecifications (part 3 of 4) notes (1) , (2) symbol conditions -5 speed grade -6 speed grade -7 speed grade unit min typ max min typ max min typ max
6?62 altera corporation stratix gx device handbook, volume 1 june 2006 high-speed i/o specification pll timing tables 6?88 through 6?90 describe the stratix gx device enhanced pll specifications. output t fall lvds 80 110 120 80 110 120 80 110 120 ps hypertransport technology 110 170 200 110 170 200 110 170 200 ps lvpecl 90 130 160 90 130 160 100 135 160 ps pcml 105 140 175 105 140 175 110 145 175 ps t duty lv d s ( j = 2 through 10) 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 % lv d s ( j =1) and lvpecl, pcml, hypertransport technology 45 50 55 45 50 55 45 50 55 % t lock all 100 100 100 s notes to table 6?87 : (1) when j = 4, 7, 8, and 10, the serdes block is used. (2) when j = 2 or j = 1, the serdes is bypassed. (3) number of parallel clk cycles. (4) number of repetitions. table 6?87. high-speed i/o s pecifications (part 4 of 4) notes (1) , (2) symbol conditions -5 speed grade -6 speed grade -7 speed grade unit min typ max min typ max min typ max table 6?88. enhanced pll spec ifications for -5 speed grades (part 1 of 2) symbol parameter min typ max unit f in input clock frequency 3 (1) 684 mhz f induty input clock duty cycle 40 60 % f einduty external feedback clock input duty cycle 40 60 % t injitter input clock period jitter 200 (2) ps t einjitter external feedback clock period jitter 200 (2) ps t fcomp external feedback clock compensation time (3) 6ns f out output frequency for internal global or regional clock 0.3 500 mhz f out_ext output frequency for external clock (2) 0.3 526 mhz
altera corporation 6?63 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics t outduty duty cycle for external clock output (when set to 50 % ) 45 55 % t jitter period jitter for external clock output (5) 100 ps for >200 mhz outclk 20 mui for <200 mhz outclk ps or mui t config5,6 time required to reconfigure the scan chains for plls 5 and 6 289/f scanclk t config11,12 time required to reconfigure the scan chains for plls 11 and 12 193/f scanclk t scanclk scanclk frequency (4) 22 mhz t dlock time required to lock dynamically (after switchover or reconfiguring any non- post-scale count ers/delays) (6) 100 s t lock time required to lock from end of device configuration 10 400 s f vco pll internal vco operating range 300 800 (7) mhz t lskew clock skew between two external clock outputs driven by the same counter 50 ps t skew clock skew between two external clock outputs driven by the different counters with the same settings 75 ps f ss spread spectrum modulation frequency 30 150 khz % spread percentage spread for spread spectrum frequency (9) 0.4 0.5 0.6 % t areset minimum pulse width on areset signal 10 ns table 6?89. enhanced pll spec ifications for -6 speed grades (part 1 of 2) symbol parameter min typ max unit f in input clock frequency 3 (1) 650 mhz f induty input clock duty cycle 40 60 % f einduty external feedback clock input duty cycle 40 60 % t injitter input clock period jitter 200 (2) ps t einjitter external feedback clock period jitter 200 (2) ps t fcomp external feedback clock compensation time (3) 6ns table 6?88. enhanced pll spec ifications for -5 speed grades (part 2 of 2) symbol parameter min typ max unit
6?64 altera corporation stratix gx device handbook, volume 1 june 2006 high-speed i/o specification f out output frequency for internal global or regional clock 0.3 450 mhz f out_ext output frequency for external clock (2) 0.3 500 mhz t outduty duty cycle for external clock output (when set to 50 % ) 45 55 % t jitter period jitter for external clock output (5) 100 ps for >200 mhz outclk 20 mui for <200 mhz outclk ps or mui t config5,6 time required to reconfigure the scan chains for plls 5 and 6 289/f scanclk t config11,12 time required to reconfigure the scan chains for plls 11 and 12 193/f scanclk t scanclk scanclk frequency (4) 22 mhz t dlock time required to lock dynamically (after switchover or reconfiguring any non- post-scale count ers/delays) (6) (10) (8) 100 s t lock time required to lock from end of device configuration (10) 10 400 s f vco pll internal vco operating range 300 800 (7) mhz t lskew clock skew between two external clock outputs driven by the same counter 50 ps t skew clock skew between two external clock outputs driven by the different counters with the same settings 75 ps f ss spread spectrum modulation frequency 30 150 khz % spread percentage spread for spread spectrum frequency (9) 0.4 0.5 0.6 % t areset minimum pulse width on areset signal 10 ns table 6?90. enhanced pll spec ifications for -7 speed grade (part 1 of 3) symbol parameter min typ max unit f in input clock frequency 3 (1) 565 mhz f induty input clock duty cycle 40 60 % f einduty external feedback clock input duty cycle 40 60 % t injitter input clock period jitter 200 (2) ps t einjitter external feedback clock period jitter 200 (2) ps table 6?89. enhanced pll spec ifications for -6 speed grades (part 2 of 2) symbol parameter min typ max unit
altera corporation 6?65 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics t fcomp external feedback clock compensation time (3) 6ns f out output frequency for internal global or regional clock 0.3 420 mhz f out_ext output frequency for external clock (2) 0.3 434 mhz t outduty duty cycle for external clock output (when set to 50 % ) 45 55 % t jitter period jitter for external clock output (5) 100 ps for >200 mhz outclk 20 mui for <200 mhz outclk ps or mui t config5,6 time required to reconfigure the scan chains for plls 5 and 6 289/f scanclk t config11,12 time required to reconfigure the scan chains for plls 11 and 12 193/f scanclk t scanclk scanclk frequency (4) 22 mhz t dlock time required to lock dynamically (after switchover or reconfiguring any non- post-scale count ers/delays) (6) (10) (8) 100 s t lock time required to lock from end of device configuration (10) 10 400 s f vco pll internal vco operating range 300 600 (7) mhz table 6?90. enhanced pll spec ifications for -7 speed grade (part 2 of 3) symbol parameter min typ max unit
6?66 altera corporation stratix gx device handbook, volume 1 june 2006 high-speed i/o specification t lskew clock skew between two external clock outputs driven by the same counter 50 ps t skew clock skew between two external clock outputs driven by the different counters with the same settings 75 ps f ss spread spectrum modulation frequency 30 150 khz % spread percentage spread for spread spectrum frequency (9) 0.5 0.6 % t areset minimum pulse width on areset signal 10 ns notes to tables 6?88 through 6?90 : (1) the minimum input cloc k frequency to the pfd (f in / n ) must be at least 3 mhz for st ratix device enhanced plls. (2) see ?maximum input & output clock rates? on page 6?54 . (3) t fcomp can also equal 50 % of the input clock period multiplied by the pre-scale divider n (whichever is less). (4) this parameter is timing analyzed by the quartus ii software because the scanclk and scandata ports can be driven by the logic array. (5) actual jitter performance may vary based on the system configuration. (6) total required time to reconfigure and lock is equal to t dlock + t config . if only post-scale co unters and delays are changed, then t dlock is equal to 0. (7) the vco range is limited to 500 to 800 mhz when the spread spectrum feature is selected. (8) lock time is a function of pll configuration and may be significantly faster dependin g on bandwidth settings or feedback counter change increment. (9) exact, user-controllable valu e depends on the pll settings. (10) the lock circuit on stratix plls does not work for industrial devices below -20c unless the pfd frequency > 200 mhz. see the stratix fpga errata sheet for more information on the pll. table 6?90. enhanced pll spec ifications for -7 speed grade (part 3 of 3) symbol parameter min typ max unit
altera corporation 6?67 june 2006 stratix gx device handbook, volume 1 dc & switching characteristics table 6?91 describes the stratix gx device fast pll specifications. table 6?91. fast pll specifications for -5 & -6 speed grade devices symbol parameter min max unit f in clkin frequency (for m = 1) (1) 300 717 mhz clkin frequency (for m = 2 to 19) 300/ m 1,000/ m mhz clkin frequency (for m = 20 to 32) 10 1,000/ m mhz f out output frequency for internal global or regional clock (2) 9.4 420 mhz f out_ext output frequency for external clock 9.375 717 mhz f vco vco operating frequency 300 1,000 mhz t induty clkin duty cycle 40 60 % t injitter period jitter for clkin pin 200 ps t duty duty cycle for dffio 1 clkout pin (3) 45 55 % t jitter period jitter for diffio clock out (3) 80 ps period jitter for internal global or regional clock 100 ps for >200-mhz outclk 20 mui for <200-mhz outclk ps or mui t lock time required for pll to acquire lock 10 100 s m multiplication factors for m counter (3) 1 32 integer l 0, l 1, g 0 multiplication factors for l 0, l 1, and g 0 counter (4) , (5) 1 32 integer t areset minimum pulse width on areset signal 10 ns table 6?92. fast pll specifications fo r -7 & -8 speed grades (part 1 of 2) symbol parameter min max unit f in clkin frequency (for m = 1) (1) , 300 640 mhz clkin frequency (for m = 2 to 19) 300/ m 700/ m mhz clkin frequency (for m = 20 to 32) 10 700/ m mhz f out output frequency for internal global or regional clock (2) 9.375 420 mhz f out_ext output frequency for external clock 9.4 500 mhz f vco vco operating frequency 300 700 mhz t induty clkin duty cycle 40 60 % t injitter period jitter for clkin pin 200 ps
6?68 altera corporation stratix gx device handbook, volume 1 june 2006 dll jitter dll jitter table 6?93 reports the jitter for the dll in the dqs phase-shift reference circuit. t duty duty cycle for dffio 1 clkout pin (3) 45 55 % t jitter period jitter for diffio clock out (3) 80 ps period jitter for internal global or regional clock 100 ps for >200 mhz outclk 20 mui for <200 mhz outclk ps or mui t lock time required for pll to acquire lock 10 100 s m multiplication factors for m counter (4) 1 32 integer l 0, l 1, g 0 multiplication factors for l 0, l 1, and g 0 counter (4) , (5) 1 32 integer t areset minimum pulse width on areset signal 10 ns notes to tables 6?91 & 6?92 : (1) see ?maximum input & output clock rates? on page 6?54 . (2) when using the serdes, high-speed differential i/o mode supports a maximum output frequency of 210 mhz to the global or regional clocks (that is, the maximum da ta rate 840 mbps divided by the smallest serdes j factor of 4). (3) this parameter is for high-spe ed differential i/o mode only. (4) these counters have a maximum of 32 if programmed for 50/50 duty cycle. otherwise, they have a maximum of 16. (5) high-speed differential i/o mode supports w = 1 to 16 and j = 4, 7, 8, or 10. table 6?92. fast pll specifications fo r -7 & -8 speed grades (part 2 of 2) symbol parameter min max unit table 6?93. dll jitter for dqs p hase shift refe rence circuit frequency (mhz) dll jitter (ps) 197 to 200 100 160 to 196 300 100 to 159 500
altera corporation 7?1 february 2005 7. reference & ordering information software stratix ? gx devices are supported by the altera ? quartus ? ii design software, which provides a comprehe nsive environment for system-on-a- programmable-chip (sopc) design. the quartus ii software includes hardware description language and schematic design entry, compilation and logic synthesis, full simulati on and advanced timing analysis, signaltap ? logic analysis, and device configuration. see the design software selector guide for more details on the quartus ii software features. the quartus ii software supports the windows 2000/nt/98, sun solaris, linux red hat v6.2 and hp-ux oper ating systems. it also supports seamless integration with indust ry-leading eda tools through the nativelink ? interface. device pin-outs device pin-outs for stratix gx devices will be released on the altera web site ( www.altera.com ). ordering information figure 7?1 describes the ordering codes for stratix gx devices. figure 7?1. stratix gx device pa ckaging ordering information devi c e type number of pa c kage type 5, 6, or 7, with 5 being the fastest number of pins for a particular fineline bga package es: f: fineline bga ep1sgx: stratix gx 10 25 40 c: commercial temperature (t j = 0? c to 85? c ) optional suffix family signature operating temperature speed grade pin count engineering sample 7 ep1sgx 40 c 1020 f gn indicates specific device options or shipment method. n: lead free trans c eiver c: 4 d: 8 f: 16 g: 20 channels i: industrial temperature (t j = -40? c to 100? c ) sgx51007-1.0
7?2 altera corporation stratix gx device handbook, volume 1 february 2005 ordering information

▲Up To Search▲

Price & Availability of EP1SGX10FF1020C6ES

	To Download EP1SGX10FF1020C6ES Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .